公开(公告)号：JP2001229676A

公开(公告)日：2001-08-24

申请号：JP2001004181

申请日：2001-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  KUHNE SEBASTIAN ,  LE THOAI-THAI

IPC: G11C11/409 ,  G11C11/407 ,  H03F3/45 ,  H03K19/0944

Abstract: PROBLEM TO BE SOLVED: To improve an integrated circuit by selecting a MOS transistor and supplying stable voltage. SOLUTION: A differential amplifier 1 has two input transistors T1, T2, a load element 2, and a current source 3 having a N channel MOS transistor T3, a section to be controlled of the transistor is connected to an input transistor and a current source supply connection terminal 31, and a control connection terminal G is connected to a connection terminal of a potential V3 being positive for a reference potential GND. An integrated circuit is inclined in a circuit device of a dynamic memory, the supply connection terminal of the current source is connected to a voltage source 4 for cutting off an array panel transistor of an integrated dynamic memory, and the voltage source has a negative potential V2 for the reference potential.

公开(公告)号：JP2002170378A

公开(公告)日：2002-06-14

申请号：JP2001249665

申请日：2001-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENEDIX ALEXANDER ,  BRAUN GEORG ,  FISCHER HELMUT ,  KLEHN BERND ,  KUHNE SEBASTIAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01F17/00 ,  H01F17/02 ,  H01F27/245 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an inductance which can be integrated monolithically and can be utilized profitably especially in an MRAM mechanism. SOLUTION: This inductance can be integrated monolithically and comprises continuous layers in which conduction layers (P1-P4) and insulation layers (I1-I3) are laminated upward and downward alternately. This constitution of the conduction layers (P1-P4) has a coil-like structure in which a center region (M) being able to provide GMR materials (WM, TB, HM) is centered.

公开(公告)号：JP2000353788A

公开(公告)日：2000-12-19

申请号：JP2000151401

申请日：2000-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUHNE SEBASTIAN

IPC: H01L21/761 ,  H01L27/08 ,  H01L27/088 ,  H01L29/786 ,  H03F3/45

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit device provided with a differential amplifier which is lessened in disadvantageous switching characteristics. SOLUTION: An integrated semiconductor circuit is possessed of a differential amplifier, which is equipped with two input transistors T1 and T2, a current source 30, and a load device 20. The NMOS transistors T1 and T2 are arranged in a P conductivity-type well, and the P conductivity-type well is arranged on a P conductivity-type substrate. The well is electrically isolated from the P conductivity-type substrate. The well is equipped with a well terminal B, and the terminal B is connected to a source terminal S. A potential difference is restrained from being produced between the well thermal B and the source terminal S, by which the switching characteristics of the transistors T1 and T2 are restrained from being affected adversely, and the switching characteristics of a differential amplifier are also restrained from being affected adversely.

公开(公告)号：DE10001371B4

公开(公告)日：2005-09-15

申请号：DE10001371

申请日：2000-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  FISCHER HELMUT ,  KUHNE SEBASTIAN

IPC: G11C11/409 ,  G11C11/407 ,  H03F3/45 ,  H03K19/0944 ,  G11C7/10 ,  H03F3/347

Abstract: An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.

公开(公告)号：DE10000758A1

公开(公告)日：2001-08-02

申请号：DE10000758

申请日：2000-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUHNE SEBASTIAN

IPC: H03K5/00 ,  H03K5/06 ,  H03K5/13 ,  H03K5/133 ,  H03K5/1534 ,  H03K5/04

Abstract: A pulse generator circuit, in particular for use in or for integrated circuits, which, in the usual way, has a number of inverting elements connected in series, a logic combining element and a delay element. A buffer circuit provided in accordance with the invention ensures that a minimum pulse length of the output pulse generated in response to the input signal is ensured even in the case of an input signal of a very short duration.

公开(公告)号：DE10128373A1

公开(公告)日：2003-01-02

申请号：DE10128373

申请日：2001-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENEDIX ALEXANDER ,  KUHNE SEBASTIAN ,  KLEHN BERND

IPC: G06F8/52 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/45 ,  G06F12/08

公开(公告)号：DE10105285A1

公开(公告)日：2002-08-29

申请号：DE10105285

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENEDIX ALEXANDER ,  KUHNE SEBASTIAN ,  KLEHN BERND

IPC: G11C7/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/407

Abstract: Semiconductor memory has a memory cell array (10) with a number of word-lines (17,18) to which at least one memory cell (11,12) is connected. A decoder (16) is used to selectively connect a word-line from a number of word-lines, depending on an address (RADR). A control device (30) drives the decoder to release the output of a non-active level on the selective word-line (17), and a reference word-line (31) is operated parallel to the selective word-line. A reference read amplifier (35) is connected to the reference memory cell (32) via at least one reference bit line (34), and an evaluation device (36) is joined to the at least reference bit line (34).

公开(公告)号：DE10001371A1

公开(公告)日：2001-08-02

申请号：DE10001371

申请日：2000-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  FISCHER HELMUT ,  KUHNE SEBASTIAN

IPC: G11C11/409 ,  G11C11/407 ,  H03F3/45 ,  H03K19/0944 ,  H03F3/347

Abstract: An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.

公开(公告)号：DE10105285B4

公开(公告)日：2008-01-10

申请号：DE10105285

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENEDIX ALEXANDER ,  KUHNE SEBASTIAN ,  KLEHN BERND

IPC: G11C11/407 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094

公开(公告)号：DE10118421C1

公开(公告)日：2002-11-07

申请号：DE10118421

申请日：2001-04-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LE THOAI-THAI ,  SCHAFFROTH THILO ,  KAISER ROBERT ,  KUHNE SEBASTIAN

IPC: H03K3/037 ,  H03K5/153

Abstract: The condition detector has two edge-triggered D-type flip-flops (10,11) controlled by different clock signals (CLKS,CLKA) for sampling a control signal (CKE) indicating the condition, coupled on the output side via respective pulse elements (12,13) to a resettable flip-flop (15), providing a feedback signal for one of the memory elements.