公开(公告)号：WO1996035129A1

公开(公告)日：1996-11-07

申请号：PCT/US1996006002

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WOOD, Alan, G. ,  FARNWORTH, Warren, M. ,  AKRAM, Salman ,  HEMBREE, David, R.

IPC: G01R31/02

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 用于测试未封装半导体晶片的方法和装置包括安装在母板（10）上的母板（10）和多个互连（12），并适于建立与芯片（14）的临时电连接。 互连（12）可以形成有用于接触管芯（14）的接合焊盘（22）的硅衬底（20）和凸起的接触构件（16）。 或者，互连（16）可以形成有安装在绝缘膜（74）上的微凸块接触构件（16）。 母板（10）允许每个模具（14）单独测试速度和功能，并且还可以使用标准老化炉并行测试。 在替代实施例中，使用母板/子板布置进行测试。 每个子板（82）包括允许骰子（14）单独测试速度和功能的互连（12）。 然后可以将多个子板（82）安装到母板（10）上，以使用标准老化烤箱进行老化测试。

公开(公告)号：WO1996025744A1

公开(公告)日：1996-08-22

申请号：PCT/US1996001756

申请日：1996-02-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  O'TOOLE, James, E.

IPC: G11C16/06

CPC classification number: G11C29/765 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52 ,  G11C29/82

Abstract: A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells. A system including a programming machine and the programmable non-volatile memory device, and methods for programming such memory devices, are also disclosed.

Abstract translation: 可编程非易失性存储器件包括可寻址存储器单元的存储器阵列和用于替换存储器阵列中的有缺陷的存储器单元的多个冗余存储器单元。 为了对存储器件进行编程，将数据写入存储器阵列中的一个或多个可寻址存储单元。 在数据未被有效地写入地址存储单元的情况下，重复尝试对相同的存储单元进行编程。 存储器件包括用于计数用于编程目的的相同存储器单元被访问次数的计数器。 当达到预定数量的这种编程周期时，确定地址存储单元是有缺陷的。 此时，冗余地址匹配电路被使能以用有效编程的冗余存储器单元替换有缺陷的存储单元。 存储器件随后将数据路由到冗余存储器单元而不是有缺陷的存储器单元。 还公开了一种包括编程机器和可编程非易失性存储器件的系统以及用于编程这种存储器件的方法。

公开(公告)号：WO1996022612A1

公开(公告)日：1996-07-25

申请号：PCT/US1996000615

申请日：1996-01-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ROBERTS, Martin, Ceredig

IPC: H01L21/8242

CPC classification number: H01L27/10844 ,  H01L27/105 ,  Y10S257/904

Abstract: A method of forming a transistor in a peripheral circuit of a random access memory device (DRAM) or a static random access memory device (SRAM) wherein a transistor gate, capacitor electrode or other component in the memory cell array is formed simultaneously with the formation of a transistor gate in the periphery.

Abstract translation: 一种在随机存取存储器件（DRAM）或静态随机存取存储器件（SRAM）的外围电路中形成晶体管的方法，其中存储单元阵列中的晶体管栅极，电容器电极或其它元件与形成同时形成 的外围的晶体管栅极。

公开(公告)号：WO1996020477A1

公开(公告)日：1996-07-04

申请号：PCT/US1995016577

申请日：1995-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MANNING, Troy, A.

IPC: G11C07/00

CPC classification number: G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/407

Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access, reset the burst length counter and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies.

Abstract translation: 集成电路存储器件设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发存取周期期间，地址在设备的内部增加，附加的地址选通转换。 每个突发访问开始时只需要一个新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问，复位突发长度计数器并初始化该设备以进行另一突发存取。 写周期时间最大化以允许突发模式工作频率的增加。

公开(公告)号：WO1996012301A1

公开(公告)日：1996-04-25

申请号：PCT/US1995012767

申请日：1995-10-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  DENNISON, Charles, H. ,  AHMAD, Aftab

IPC: H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/8238 ,  H01L27/105

Abstract: This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. The focus of this invention is a CMOS manufacturing process flow which permits P-channel source/drain doping subsequent to capacitor formation. A main feature of the process is the deposition and planarization of a thick insulative mold layer subsequent to N-channel device patterning, but prior to P-channel device patterning. In one embodiment of the process, portions of this insulative layer overlying the P-channel transistor regions are removed during the storage-node contact etch. Thus, a low-aspect-ratio etch can be employed to pattern P-channel devices, and a blanket P+ implant may be performed without implanting the P-type impurity into source/drain regions of the N-channel devices. Another important feature of the invention is the incorporation of P-channel gate sidewall spacers and offset P-channel implants into the process flow.

Abstract translation: 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。 本发明的重点是CMOS制造工艺流程，其允许电容器形成之后的P沟道源极/漏极掺杂。 该工艺的主要特征是在N沟道器件图案化之后，但在P沟道器件图案化之前，沉积和平坦化厚的绝缘模具层。 在该过程的一个实施例中，在存储节点接触蚀刻期间，去除覆盖在P沟道晶体管区域上的该绝缘层的部分。 因此，可以采用低纵横比蚀刻图案P沟道器件，并且可以执行覆盖P +注入而不将P型杂质注入到N沟道器件的源极/漏极区域中。 本发明的另一个重要特征是将P沟道栅极侧壁间隔物和偏移P沟道植入物结合到工艺流程中。

公开(公告)号：WO1996012286A1

公开(公告)日：1996-04-25

申请号：PCT/US1995012677

申请日：1995-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HUSH, Glen, E. ,  CASPER, Stephen, L.

IPC: G11C07/00

CPC classification number: G11C7/1075

Abstract: A multi-port memory device includes a row-column array, a random access port, a plurality of bidirectional serial access memory (SAM) ports, and a switching network for coupling SAM ports to sets of columns. A column is defined as a number of memory cells sharing a sense amplifier. Sets of columns are defined in one rectangular region or among several rectangular regions of the array. The switching network selectively couples each SAM port with each set, each set with each other set, and each SAM port with each other SAM port. A video random access memory (VRAM) or a multi-port dynamic random access memory (DRAM) of the present invention provides increased flexibility in smaller die area.

Abstract translation: 多端口存储器件包括行列阵列，随机存取端口，多个双向串行存取存储器（SAM）端口，以及用于将SAM端口耦合到列组的交换网络。 列被定义为共享读出放大器的多个存储单元。 列的集合在一个矩形区域或阵列的几个矩形区域中定义。 交换网络将每个SAM端口与每个集合选择性地耦合，每个集合彼此设置，并且每个SAM端口与彼此的SAM端口。 本发明的视频随机存取存储器（VRAM）或多端口动态随机存取存储器（DRAM）提供了在较小管芯区域中增加的灵活性。

公开(公告)号：WO1995033264A1

公开(公告)日：1995-12-07

申请号：PCT/US1995007029

申请日：1995-06-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MERRITT, Todd

IPC: G11C11/40

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  H03K19/09429

Abstract: For use in a semiconductor circuit device, a uniquely-arranged tri-state output buffer (12) responds to a control signal generated in the semiconductor circuit device and a below-ground voltage level at an output terminal to prevent wasted drain current and substrate current, and reduce capacitance at the pull-up node driving the output terminal. The output buffer includes a power supply signal providing at least one voltage level with respect to common; an output terminal; a first circuit responding to the control signal by providing a first control voltage on a pull-up node; and a second circuit responding to the control signal by providing a second control voltage on a pull-down node. Further, the output buffer includes a pull-up transistor (60), responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a pull-down transistor (50), responsive to the voltage on the pull-down node and coupled between common and the output terminal.

Abstract translation: 为了在半导体电路器件中使用，唯一排列的三态输出缓冲器（12）对半导体电路器件中产生的控制信号和输出端子处的地电压进行响应，以防止浪费的漏极电流和衬底电流 并且降低驱动输出端子的上拉节点处的电容。 输出缓冲器包括相对于公共端提供至少一个电压电平的电源信号; 输出端子; 通过在上拉节点上提供第一控制电压来响应所述控制信号的第一电路; 以及通过在下拉节点上提供第二控制电压来响应于所述控制信号的第二电路。 此外，输出缓冲器包括上拉晶体管（60），响应于上拉节点上的电压并耦合在电源信号和输出端之间; 一个下拉晶体管（50），响应于下拉节点上的电压并耦合在公共端和输出端之间。

公开(公告)号：WO1995031042A1

公开(公告)日：1995-11-16

申请号：PCT/US1995005537

申请日：1995-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul ,  MANNING, Troy

IPC: H03K19/003

CPC classification number: H03K19/01742 ,  H03K19/00361

Abstract: To compensate for leakage current resulting from parasitic resistance, an integrated circuit device includes a boosting current pump (30) to continuously boost the input of an NMOS output circuit (24) so long as the output circuit is providing a logic high output signal. The NMOS output circuit (24) has an input for receiving an input signal and an output for driving at least one output signal line. An oscillation circuit (22) provides an oscillating digital signal to the boosting current pump (30). The pump (30) responds to the oscillating digital signal and to the input signal being in one of two predetermined states to provide additional current at the input of the NMOS output circuit (24) to compensate for the leakage current.

Abstract translation: 为了补偿由寄生电阻引起的泄漏电流，集成电路器件包括升压电流泵（30），只要输出电路提供逻辑高输出信号，就连续升压NMOS输出电路（24）的输入。 NMOS输出电路（24）具有用于接收输入信号的输入端和用于驱动至少一个输出信号线的输出端。 振荡电路（22）向升压电流泵（30）提供振荡数字信号。 泵（30）响应于振荡数字信号和输入信号处于两个预定状态之一，以在NMOS输出电路（24）的输入处提供额外的电流，以补偿漏电流。

公开(公告)号：WO1992008230A1

公开(公告)日：1992-05-14

申请号：PCT/US1991008057

申请日：1991-10-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HESSON, James, H.

IPC: G11C07/00

CPC classification number: G11C8/16

Abstract: A memory register file array addressable in both word and doubleword format has memory cells of a feedback-type latch variety, having at least two tri-state inverter paths (WP1 and WP2) for the input of data, and at least two tri-state inverter paths (RP1, RP2 and RP3) for the output of data. A tri-state inverter (53) provides the feedback within each array cell. This feedback inverter is tri-stated during each write operation, thus increasing circuit speed and permitting simultaneous read and write operations to be performed on the same cell during a single machine cycle. Error correction is performed during format decode and format operations so that error correction code (ECC) syndrome bit generation can occur in parallel with formatting. Improved clocking operations maintain symmetry of the register file clock signals and provide high clock skew tolerance. Tri-state isolation buffers (4, 5, 6, 7, 8 and 9) are used to reduce read access time.

Abstract translation: 可以以字和双字格式寻址的存储器寄存器文件阵列具有反馈型锁存器种类的存储单元，具有用于输入数据的至少两个三态反相器路径（WP1和WP2），以及至少两个三态 逆变器路径（RP1，RP2和RP3）用于输出数据。 三态逆变器（53）在每个阵列单元内提供反馈。 在每个写入操作期间，该反馈反馈器是三态的，从而提高电路速度，并允许在单个机器周期内在同一个单元上执行同时的读取和写入操作。 在格式化解码和格式化操作期间执行错误校正，以便与格式化并行发生纠错码（ECC）校验码位产生。 改进的时钟操作保持寄存器文件时钟信号的对称性，并提供高时钟偏移容限。 三态隔离缓冲器（4,5,6,7,8和9）用于减少读访问时间。

公开(公告)号：WO1998031017A1

公开(公告)日：1998-07-16

申请号：PCT/US1997023801

申请日：1997-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC: G11C07/00

CPC classification number: H03K17/164 ,  G11C7/1051

Abstract: An output driver circuit is described which offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtain different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry are described for improving high frequency operation.

Abstract translation: 描述了一种输出驱动器电路，其提供用于诸如同步动态随机存取存储器（SDRAM）的同步存储器中的高速数据通信的控制和逻辑电平调整。 电平调节通过端接电阻之间的电阻分压和输出节点与VDD和VSS电源之间的可控阻抗获得。 响应于输入信号的转变，控制功能包括输出节点处的信号的转换速率修改。 输出晶体管的不同加权方案获得输出信号的不同特性。 描述负载匹配电路和电压电平强制电路以改善高频操作。