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    93.
    发明专利
    未知

    公开(公告)号：DE602006008738D1

    公开(公告)日：2009-10-08

    申请号：DE602006008738

    申请日：2006-05-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C8/08 ,  G11C16/12

    Abstract: A circuit is disclosed. The circuit comprises a first input terminal (INA1), a second input terminal (INA2) and an output terminal (OUT). The circuit further includes a first circuital branch (610) connected between the first input terminal and the output terminal, and a second circuital branch (620) connected between the second input terminal and the output terminal. The first circuital branch is selectively activatable for coupling the first input terminal with the output terminal, and the second circuital branch is selectively activatable for coupling the second input terminal with the output terminal. The first and second circuital branches comprise each at least one electronic device having at least a first and a second device terminals. Said at least one electronic device is designed to guarantee the capability of sustaining voltage differences across at least the first and second device terminals thereof that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively.

    94.
    发明专利
    未知

    公开(公告)号：DE602006006029D1

    公开(公告)日：2009-05-14

    申请号：DE602006006029

    申请日：2006-04-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C16/24 ,  G11C7/12 ,  G11C8/10

    Abstract: A column decoding system (140,150) for selectively biasing bit lines (BLij) of a non-volatile memory device (100) is disclosed. The bit lines are logically grouped into at least one packet (PBL). For each packet, the column decoding system includes a plurality of selection paths each one for applying a biasing voltage to a corresponding bit line, each path including a plurality of series-connected selection transistors (Mi,Mij,Pij) each one having a threshold voltage, and selection means for selecting a path (M1,M11,P11) corresponding to a selected bit line (BL11), the selection means including means for biasing at least one transistor (P12) in each non-selected path (M1,M12,P12) to an open condition to have the corresponding non-selected bit line (BL12) floating; the selection means further includes means for biasing at least one other transistor (M12) in each non-selected path to a drop condition to introduce a voltage drop in the non-selected path higher than the threshold voltage of said one transistor (P12) in absolute value.

    95.
    发明专利
    未知

    公开(公告)号：DE60129786D1

    公开(公告)日：2007-09-20

    申请号：DE60129786

    申请日：2001-01-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C11/56 ,  G11C7/06 ,  G11C16/06 ,  G11C16/02 ,  G11C16/26

    Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell (36) by a capacitive element (22, 23). The capacitive element (22, 23) is initially charged and then discharged linearly in a preset time, while the memory cell (36) is biased at a constant voltage. In a first operating mode, initially a first capacitor (22) and a second capacitor (23) are respectively charged to a first charge value and to a second charge value. The second capacitor (23) is discharged through the memory cell (36) at a constant current in a preset time; the first charge is shared between the first capacitor (22) and the second capacitor (23); and then the shared charge is measured.

    96.
    发明专利
    未知

    公开(公告)号：DE69629669T2

    公开(公告)日：2004-07-08

    申请号：DE69629669

    申请日：1996-06-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO

    IPC: G11C16/28 ,  G11C16/06

    Abstract: The read circuit presents a current mirror circuit (9) including a first and second load transistor (12, 13) interposed between the supply line (15) and a respective first and second output node (16, 17); the first output node (16) is connected to a cell (4) to be read; the second output node (17) is connected to a generating stage (20, 51) generating a reference current (IR1) having a predetermined characteristic; and the size of the second load transistor (13) is N times greater than the first load transistor (12). To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit (55) presents a current balancing branch (75) connected between the first output node (16) and ground for generating an equalizing current (IB) presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

    97.
    发明专利
    未知

    公开(公告)号：DE69632580D1

    公开(公告)日：2004-07-01

    申请号：DE69632580

    申请日：1996-07-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  GHILARDELLI ANDREA

    IPC: G11C7/10 ,  G11C7/00

    Abstract: The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage (10) of the pull-up/pull-down type made up of a complementary pair of transistors (Mu,Md) inserted between a primary reference supply voltage (Vcc) and a secondary reference voltage (GND) and a voltage regulator (11) for the control terminals (O1,O2) of said transistors. The regulator (11) is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage (10) by boosting the voltage applied to said control terminals (O1,O2).

    99.
    发明专利
    未知

    公开(公告)号：DE69631123D1

    公开(公告)日：2004-01-29

    申请号：DE69631123

    申请日：1996-06-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  RINO MICHELONI ,  COMMODARO STEFANO

    IPC: G11C16/06 ,  G11C16/28

    Abstract: The read circuit (30) has an array branch (31) connected to an array cell (33), and a reference branch (32) connected to a reference cell (37); the array branch (31) presents an array load transistor (42) interposed between a supply line (36) and the array cell (33), and the reference branch (32) presents a reference load transistor (43) interposed between the supply line (36) and the reference cell (37); and the array and reference load transistors (42, 43) form a current mirror wherein the array load transistor (42) is diode-connected and presents a first predetermined channel width/length ratio (W1/L1), and the reference load transistor (43) presents a second predetermined channel width/length ratio (W2/L2) N times greater than the first ratio (W1/L1), so that the current (I'M) flowing in the array cell (33) is supplied, amplified, to the reference branch.

    100.
    发明专利
    未知

    公开(公告)号：DE69630024D1

    公开(公告)日：2003-10-23

    申请号：DE69630024

    申请日：1996-06-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  COMMODARO STEFANO

    IPC: G11C16/28 ,  G11C16/06

    Abstract: A nonvolatile memory (35) presenting a data memory array (2) including memory cells 85); a read circuit (40) including a plurality of sense amplifiers (10), each connected to a respective array branch (17) to be connected to the memory cells; and a reference generating circuit (55) including a single reference cell (60) arranged outside the data memory array (2) and generating a reference signal (IR). The reference generating circuit (55) presents a plurality of reference branches (41), each connected to a respective sense amplifier (10); and current mirror circuits (53, 54, 62, 63) interposed between the reference cell (60) and the reference branches (41), and supplying the reference branches with the reference signal (IR).

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