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公开(公告)号：DE69630363D1
公开(公告)日：2003-11-20
申请号：DE69630363
申请日：1996-05-24
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO , COMMODARO STEFANO
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公开(公告)号：IT1316870B1
公开(公告)日：2003-05-12
申请号：ITMI20000687
申请日：2000-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , COMMODARO STEFANO , PICCA MASSIMILIANO , MONGELLI PATRIZIA
IPC: G11C29/56
Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.
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公开(公告)号：DE69621020D1
公开(公告)日：2002-06-06
申请号：DE69621020
申请日：1996-11-04
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE MARCO , ZAMMATTIO MATTEO , COMMODARO STEFANO
Abstract: A band-gap reference voltage generator comprises an operational amplifier (2) comprising a first input and a second input, the first input being coupled to a first feedback network (4) and the second input being coupled to a second feedback network (6) both coupled to an output (7) of the operational amplifier providing a reference voltage, the first feedback network containing an emitter-base junction of first bipolar junction transistor means (Q1) and the second feedback network containing an emitter-base junction of second bipolar junction transistor means (Q2), and current supplying means (11) for supplying a bias current to the operational amplifier, the current supplying means being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off, characterized by comprising start-up circuit means (13) activated upon start-up of the reference voltage generator for a fixed, prescribed time interval for forcing a start-up current to flow through the first bipolar junction transistor means (Q1).
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公开(公告)号：DE69631123D1
公开(公告)日：2004-01-29
申请号：DE69631123
申请日：1996-06-18
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , RINO MICHELONI , COMMODARO STEFANO
Abstract: The read circuit (30) has an array branch (31) connected to an array cell (33), and a reference branch (32) connected to a reference cell (37); the array branch (31) presents an array load transistor (42) interposed between a supply line (36) and the array cell (33), and the reference branch (32) presents a reference load transistor (43) interposed between the supply line (36) and the reference cell (37); and the array and reference load transistors (42, 43) form a current mirror wherein the array load transistor (42) is diode-connected and presents a first predetermined channel width/length ratio (W1/L1), and the reference load transistor (43) presents a second predetermined channel width/length ratio (W2/L2) N times greater than the first ratio (W1/L1), so that the current (I'M) flowing in the array cell (33) is supplied, amplified, to the reference branch.
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Patent Agency Ranking
公开(公告)号：DE69630024D1
公开(公告)日：2003-10-23
申请号：DE69630024
申请日：1996-06-18
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO , COMMODARO STEFANO
Abstract: A nonvolatile memory (35) presenting a data memory array (2) including memory cells 85); a read circuit (40) including a plurality of sense amplifiers (10), each connected to a respective array branch (17) to be connected to the memory cells; and a reference generating circuit (55) including a single reference cell (60) arranged outside the data memory array (2) and generating a reference signal (IR). The reference generating circuit (55) presents a plurality of reference branches (41), each connected to a respective sense amplifier (10); and current mirror circuits (53, 54, 62, 63) interposed between the reference cell (60) and the reference branches (41), and supplying the reference branches with the reference signal (IR).
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公开(公告)号：DE69621020T2
公开(公告)日：2002-10-24
申请号：DE69621020
申请日：1996-11-04
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE MARCO , ZAMMATTIO MATTEO , COMMODARO STEFANO
Abstract: A band-gap reference voltage generator comprises an operational amplifier (2) comprising a first input and a second input, the first input being coupled to a first feedback network (4) and the second input being coupled to a second feedback network (6) both coupled to an output (7) of the operational amplifier providing a reference voltage, the first feedback network containing an emitter-base junction of first bipolar junction transistor means (Q1) and the second feedback network containing an emitter-base junction of second bipolar junction transistor means (Q2), and current supplying means (11) for supplying a bias current to the operational amplifier, the current supplying means being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off, characterized by comprising start-up circuit means (13) activated upon start-up of the reference voltage generator for a fixed, prescribed time interval for forcing a start-up current to flow through the first bipolar junction transistor means (Q1).
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公开(公告)号：DE69619972D1
公开(公告)日：2002-04-25
申请号：DE69619972
申请日：1996-06-18
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO , COMMODARO STEFANO
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公开(公告)号：ITMI20000687A1
公开(公告)日：2001-10-01
申请号：ITMI20000687
申请日：2000-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： COMMODARO STEFANO , CAMPARDO GIOVANNI , PICCA MASSIMILIANO , MONGELLI PATRIZIA
IPC: G11C29/56
Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.
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公开(公告)号：ITMI20000687D0
公开(公告)日：2000-03-31
申请号：ITMI20000687
申请日：2000-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： COMMODARO STEFANO , CAMPARDO GIOVANNI , PICCA MASSIMILIANO , MONGELLI PATRIZIA
IPC: G11C29/56
Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.
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