-
公开(公告)号：KR100488099B1
公开(公告)日：2005-05-06
申请号：KR1020020071498
申请日：2002-11-18
Applicant: 한국전자통신연구원
CPC classification number: H01L29/66621 , H01L21/2255 , H01L29/66553 , H01L29/7834
Abstract: 본 발명의 모오스 트랜지스터 구조는 기존의 상보성 모오스 트랜지스터 기술로 제작된다. 나노미터 급의 모오스 트랜지스터 제작 방법에 있어서 특수한 리소그래피 기술을 사용하지 않고, 스페이서 폭을 조절하여 나노미터 급의 게이트를 형성한다. 도핑된 스페이서를 사용하여 매우 얕은 접합의 소스, 드레인 확장 영역을 형성할 수 있으며, 이는 종래의 이온주입에 의한 기판의 손상을 방지한다. 열처리 과정을 통하여 도핑된 스페이서로부터 반도체 기판으로 도펀트가 확산되어 매우 얕은 접합을 갖는 소스/드레인 확장 영역을 형성할 수 있다.
-
公开(公告)号：KR1020050007658A
公开(公告)日：2005-01-21
申请号：KR1020030047184
申请日：2003-07-11
Applicant: 한국전자통신연구원
IPC: G09G3/30
CPC classification number: G09G3/3283 , G09G3/3241 , G09G2310/027 , G09G2330/021
Abstract: PURPOSE: A low power and high density source driver and a current driven active matrix organic electroluminescence device provided with the same are provided to increase the degree of integration by operating the inner circuits of the driver with a normal voltage. CONSTITUTION: A low power and high density source driver includes a shift register unit(310), a data latch unit(320), a line latch unit(330), a current digital-to-analog converter(340) and a high voltage protection unit(350). The shift register unit outputs the enable signal for storing the data. The data latch unit stores the digital data inputted from outside. The line latch unit outputs the stored data in parallel simultaneously. The current digital-to-analog converter converts the digital signal outputted from the line latch unit and outputs the converted signal as the current signal. And, the high voltage protection unit transmits the outputs the outputs of the current digital-to-analog converter to the source line of the external panel and protects the inner circuits from the high voltage of the panel side.
Abstract translation: 目的：提供一种低功率和高密度源极驱动器及其驱动的驱动有源矩阵有机电致发光器件，以通过以正常电压操作驱动器的内部电路来增加集成度。 构成：低功率和高密度源驱动器包括移位寄存器单元（310），数据锁存单元（320），线锁存单元（330），当前数模转换器（340）和高电压 保护单元（350）。 移位寄存器单元输出用于存储数据的使能信号。 数据锁存单元存储从外部输入的数字数据。 线路锁存单元同时并行输出存储的数据。 当前的数/模转换器转换从线锁存单元输出的数字信号，并输出转换的信号作为电流信号。 而且，高电压保护单元将输出的当前数模转换器的输出发送到外部面板的源极线，并保护内部电路免受面板侧的高压。
-
公开(公告)号：KR100453821B1
公开(公告)日：2004-10-20
申请号：KR1020020061487
申请日：2002-10-09
Applicant: 한국전자통신연구원
IPC: G06F13/38
CPC classification number: G06F13/4217 , Y02D10/14 , Y02D10/151
Abstract: 본 발명의 마이크로 컨트롤러를 위한 데이터 버스 시스템은, 입/출력부, 중앙 처리 장치, 내부 메모리 및 주변 회로부를 포함하는 마이크로 컨트롤러를 위한 데이터 버스 시스템에 관한 것이다. 이 데이터 버스 시스템은, 중앙 처리 장치로부터 나가는 데이터와 외부로부터 입/출력부 또는 내부 메모리로 들어가는 데이터에 의해 사용되는 외부 억세스 버스와, 중앙 처리 장치로 들어가는 데이터와 입/출력부 또는 내부 메모리로부터 나가는 데이터와, 그리고 주변 회로부로 들어가거나 주변 회로부로부터 나가는 데이터에 의해 사용되는 내부 억세스 버스, 및 내부 메모리가 입/출력부로 통해 나가는 데이터에 의해 사용되는 내부 메모리 테스트 버스를 구비한다.
Abstract translation: 提供一种用于微控制器的数据总线系统，其具有输入/输出（I / O）单元，中央处理单元（CPU），内部存储器单元和外围电路。 数据总线系统包括当从CPU输出数据或将数据输入到I / O单元或内部存储单元时使用的外部访问总线; 当数据输入到CPU时使用的内部访问总线，从I / O单元或内部存储单元输出数据，或者数据输入到外围电路或从外围电路输出数据; 以及内部存储器测试总线，用于从内部存储器单元输出数据并将其输入到I / O单元。
-
公开(公告)号：KR1020040019484A
公开(公告)日：2004-03-06
申请号：KR1020020051029
申请日：2002-08-28
Applicant: 한국전자통신연구원
IPC: H03K19/00
CPC classification number: H03K19/0016
Abstract: PURPOSE: An input/output port circuit is provided, which is driven by high supply voltage and low supply voltage at the same time, and reduces power consumption by selectivly driving the input/output port circuit. CONSTITUTION: A signal register(22) stores output signals, and an input/output register(23) stores an input/output control signal determining an input/output direction. A power supply switch circuit(21) supplies a high voltage or a low voltage selectively according to a control signal. A signal control circuit(24) determines a direction of a signal according to a value of the signal register and a value of the input/output register. An output control circuit(25) is driven according to a value of the control register and an output of the signal control circuit. And an output driver circuit(26) outputs the low voltage and the high voltage or a ground value according to outputs of the signal control circuit and the output control circuit. The input/output port circuit comprises a number of output control registers(27).
Abstract translation: 目的：提供输入/输出端口电路，同时由高电源电压和低电源电压驱动，并通过选择性驱动输入/输出端口电路降低功耗。 构成：信号寄存器（22）存储输出信号，输入/输出寄存器（23）存储确定输入/输出方向的输入/输出控制信号。 电源开关电路（21）根据控制信号选择性地提供高电压或低电压。 信号控制电路（24）根据信号寄存器的值和输入/输出寄存器的值确定信号的方向。 根据控制寄存器的值和信号控制电路的输出来驱动输出控制电路（25）。 并且输出驱动电路（26）根据信号控制电路和输出控制电路的输出输出低电压和高电压或接地值。 输入/输出端口电路包括多个输出控制寄存器（27）。
-
公开(公告)号：KR100417006B1
公开(公告)日：2004-02-05
申请号：KR1020010066228
申请日：2001-10-26
Applicant: 한국전자통신연구원
IPC: H02M3/28
Abstract: PURPOSE: A multi-output DC-DC converter is provided to be capable of outputting a multi-level voltage using one embedded inductor having a plurality of output taps. CONSTITUTION: An inductor part(300) is supplied with an input voltage and has a plurality of output taps which are spaced apart from each other. The first switching unit(230) consists of a plurality of transistors cascaded between each output tap of the inductor part and a common node and controlled by corresponding control signals. The second switching unit(210) is connected between the common node and the output terminal and is controlled by the control signal. The third switching unit(220) consists of a plurality of transistors which are connected in parallel between the common node and a ground voltage and are selectively operated according to corresponding control signals.
Abstract translation: 目的：提供一种多输出DC-DC转换器，其能够使用具有多个输出抽头的一个嵌入式电感器来输出多电平电压。 构成：电感器部件（300）被提供有输入电压并且具有彼此间隔开的多个输出抽头。 第一开关单元（230）由级联在电感器部分的每个输出抽头和公共节点之间的多个晶体管构成，并由相应的控制信号控制。 第二开关单元（210）连接在公共节点和输出端之间并由控制信号控制。 第三开关单元（220）包括并联连接在公共节点和地电压之间的多个晶体管，并且根据相应的控制信号选择性地操作。
-
Patent Agency Ranking
公开(公告)号：KR100400079B1
公开(公告)日：2003-09-29
申请号：KR1020010062350
申请日：2001-10-10
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/7813 , H01L29/41766 , H01L29/41775 , H01L29/7802
Abstract: A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.
Abstract translation: 提供了一种用于制造具有沟槽栅极结构的功率半导体器件的方法。 在具有高浓度的第一导电类型的半导体衬底上顺序地形成具有低浓度的第一导电类型的外延层和具有第二导电类型的本体区域。 在体区上形成氧化层图案。 使用氧化物层图案作为蚀刻掩模来形成第一沟槽，以穿透具有第一厚度的本体区域的预定部分。 使用氧化物层图案作为离子注入掩模，通过杂质离子注入围绕第一沟槽形成具有高浓度的第二导电类型的体接触区域。 形成第一间隔层以覆盖第一沟槽的侧壁和氧化物层图案的侧壁。 使用氧化物层图案和第一间隔物层作为蚀刻掩模来形成第二沟槽，以穿透具有比第一厚度大的第二厚度的本体区域的预定部分。 通过使用氧化物层图案和第一间隔层作为离子注入掩模的杂质离子注入来形成具有高浓度的第一导电类型的源极区域以围绕第二沟槽。 形成第二间隔层以覆盖第二沟槽的侧壁和第一间隔层的侧壁。 使用氧化物层图案，第一间隔物层和第二间隔物层作为蚀刻掩模，将第三沟槽形成至外延层的预定深度。 栅极绝缘层形成在第三沟槽中。 栅极导电图案形成在栅极绝缘层中。 在栅极导电层图案上形成氧化物层。 第一和第二间隔层被去除。 第一金属电极层形成为电连接到源极区和体接触区。 第二金属电极层被形成为与栅极导电层图案电连接。 形成第三金属电极层以电连接到半导体衬底。
-
公开(公告)号：KR1020030054758A
公开(公告)日：2003-07-02
申请号：KR1020010085165
申请日：2001-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/76
CPC classification number: H01L27/1203 , H01L21/84
Abstract: PURPOSE: A method for fabricating a power IC is provided to reduce an isolation area by forming a nitride layer between a trench oxide layer and a polysilicon layer or performing a trench isolation process using the nitride layer and the polysilicon instead of the trench oxide layer. CONSTITUTION: An oxide layer and a photoresist layer are sequentially on a silicon layer(102). The photoresist layer is patterned by using a trench mask. The oxide layer is patterned by using the patterned photoresist layer as a mask. The remaining photoresist is removed therefrom. The trench is etched by using the patterned oxide layer as the mask and a trench is formed thereby. A nitride layer(134) is formed on an upper surface of the resultant including the trench. The trench is buried by depositing a polysilicon thereon. An isolation layer is formed by removing the polysilicon and the nitride layer.
Abstract translation: 目的：提供一种用于制造功率IC的方法，通过在沟槽氧化物层和多晶硅层之间形成氮化物层或者使用氮化物层和多晶硅代替沟槽氧化物层来执行沟槽隔离工艺来减小隔离区域。 构成：氧化物层和光致抗蚀剂层顺序地在硅层（102）上。 通过使用沟槽掩模来对抗蚀剂层进行构图。 通过使用图案化的光致抗蚀剂层作为掩模来对氧化物层进行构图。 从中除去剩余的光致抗蚀剂。 通过使用图案化氧化物层作为掩模来蚀刻沟槽，由此形成沟槽。 在包括沟槽的结果的上表面上形成氮化物层（134）。 通过在其上沉积多晶硅来掩埋沟槽。 通过去除多晶硅和氮化物层形成隔离层。
-
公开(公告)号：KR100388063B1
公开(公告)日：2003-06-27
申请号：KR1020000078264
申请日：2000-12-19
Applicant: 한국전자통신연구원
IPC: H01L27/04
Abstract: PURPOSE: A method for fabricating a power integrated circuit is provided to remarkably reduce a high temperature annealing process for fabricating the power integrated circuit, by mixing a non-reduced surface field(RESURF) n-lateral double diffused metal oxide semiconductor(LDMOS) transistor and a RESURF p-LDMOS transistor. CONSTITUTION: The power integrated circuit includes the RESURF LDMOS transistor using a silicon-on-insulator, the non-RESURF LDMOS transistor of an opposite type to the RESURF LDMOS transistor and a logic complementary metal oxide semiconductor(CMOS). The regions where the logic CMOS as a low voltage device and an LDMOS transistor as a high power device are fabricated are doped with the same impurity type in a silicon substrate.
Abstract translation: 目的：提供一种用于制造功率集成电路的方法，以通过混合非减小表面场（RESURF）n型横向双扩散金属氧化物半导体（LDMOS）晶体管来显着减少用于制造功率集成电路的高温退火工艺 和RESURF p-LDMOS晶体管。 构成：功率集成电路包括使用绝缘体上硅的RESURF LDMOS晶体管，与RESURF LDMOS晶体管和逻辑互补金属氧化物半导体（CMOS）相反类型的非RESURF LDMOS晶体管。 作为低电压器件的逻辑CMOS和作为高功率器件的LDMOS晶体管被制造的区域在硅衬底中掺杂有相同的杂质类型。
-
公开(公告)号：KR100385858B1
公开(公告)日：2003-06-02
申请号：KR1020000082804
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: H01L27/092
Abstract: PURPOSE: A power device having a trench drain field plate is provided to control extension of space charges at the edge of a gate by including a trench structure in a drift region, and to obtain a breakdown voltage and a low on-resistance by improving reduced surface field(RESURF) effect. CONSTITUTION: A buried layer of the first conductivity type and the epi layer of the second conductivity type are formed on a silicon substrate. A diffusion layer of the first conductivity type as a channel portion is formed on the buried layer. The drift region of the second conductivity type is partially formed on the epi layer. A gate insulation layer is partially formed in the diffusion layer and the drift region. A part of the drift region is formed of a trench structure so that the edge of the gate partially extends in the trench. A drain field plate is formed on an insulation layer having a thickness different from that of the gate insulation layer, connected from the inside of the trench to a drain.
Abstract translation: 目的：提供一种具有沟槽漏极场板的功率器件，以通过在漂移区中包括沟槽结构来控制栅极边缘处的空间电荷的扩展，并且通过改进还原而获得击穿电压和低导通电阻 表面场（RESURF）效应。 构成：在硅衬底上形成第一导电类型的埋层和第二导电类型的外延层。 在掩埋层上形成作为沟道部分的第一导电类型的扩散层。 第二导电类型的漂移区部分形成在外延层上。 栅绝缘层部分地形成在扩散层和漂移区中。 漂移区的一部分由沟槽结构形成，使得栅极的边缘部分地在沟槽中延伸。 漏极场板形成在厚度不同于栅极绝缘层的绝缘层上，从沟槽内部连接到漏极。
-
-
-
-
-
-
-
-
-
Search Results
230
records
(took 0.029 seconds)
