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公开(公告)号：KR1020120071488A
公开(公告)日：2012-07-03
申请号：KR1020100133053
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: H01L21/60 , H01L21/306
CPC classification number: H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A fabrication method of backside via holes on a semiconductor substrate is provided to ensure electrical connection from a back side of a substrate to a pad of a front side by uniformly depositing a base metal on a cross section of a via hole. CONSTITUTION: A pad consisting of nickel(102) and gold(103) is formed on a front side of a semiconductor substrate(101). A metal layer is deposited on a back side of the substrate. The deposition of the metal layer is performed by electron-beam deposition, sputtering, or plating. Photoresist having an inclined cross section is applied on the metal layer. The photoresist and the metal layer are simultaneously etched.
Abstract translation: 目的：提供半导体基板上的背面通孔的制造方法，以通过在通孔的横截面上均匀地沉积基底金属来确保从基板的背面到前侧的焊盘之间的电连接。 构成：在半导体衬底（101）的前侧形成由镍（102）和金（103）组成的衬垫。 金属层沉积在基板的背面。 金属层的沉积通过电子束沉积，溅射或电镀进行。 具有倾斜横截面的光刻胶施加在金属层上。 同时蚀刻光致抗蚀剂和金属层。
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公开(公告)号：KR1020110067929A
公开(公告)日：2011-06-22
申请号：KR1020090124720
申请日：2009-12-15
Applicant: 한국전자통신연구원
CPC classification number: H01F17/0006 , H01F2017/0086 , H01L28/10
Abstract: PURPOSE: An inductor is provided to be mounted on a semiconductor substrate with a small area by using first to fourth vertical conductive units. CONSTITUTION: A first conductive line is electrically connected to a second conductive terminal(140b) and a third conductive terminal(140c). A second conductive line is electrically connected to a first conductive terminal(140a) and a fourth conductive terminal(140d). A third conductive line is electrically connected to the first conductive terminal and the third conductive terminal.
Abstract translation: 目的：通过使用第一至第四垂直导电单元，提供以小面积安装在半导体衬底上的电感器。 构成：第一导电线电连接到第二导电端子（140b）和第三导电端子（140c）。 第二导电线电连接到第一导电端子（140a）和第四导电端子（140d）。 第三导线与第一导电端子和第三导电端子电连接。
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公开(公告)号：KR1020100064588A
公开(公告)日：2010-06-15
申请号：KR1020080123093
申请日：2008-12-05
Applicant: 한국전자통신연구원
CPC classification number: H01L29/7304 , H01L29/66272 , H01L29/732
Abstract: PURPOSE: A compound semiconductor bipolar transistor and a forming method thereof are provided to improve the stability of a device by directly forming a capacitor on a base layer not the outside of the device. CONSTITUTION: A collector layer(112) is arranged on a substrate. A base layer is arranged on the collector layer. An emitter layer is formed on the base layer and covers a part of the base layer. A bottom electrode(122a) is contacted with the base layer. A pair of resistance electrodes are arranged on the base layer. A dielectric layer covers the bottom electrode. A top electrode(150) faces the bottom electrode and is arranged on the dielectric layer.
Abstract translation: 目的：提供一种化合物半导体双极晶体管及其形成方法，以通过在基底层而不是设备外部直接形成电容器来提高器件的稳定性。 构成：集电极层（112）布置在基板上。 基层设置在集电极层上。 发射极层形成在基底层上并覆盖基底层的一部分。 底部电极（122a）与基底层接触。 一对电阻电极布置在基层上。 电介质层覆盖底部电极。 顶部电极（150）面向底部电极并布置在电介质层上。
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公开(公告)号：KR1020100061608A
公开(公告)日：2010-06-08
申请号：KR1020080120193
申请日：2008-11-29
Applicant: 한국전자통신연구원
IPC: H01L29/737 , H01L29/73
CPC classification number: H01L29/42304 , H01L29/41708 , H01L29/66318 , H01L29/7371
Abstract: PURPOSE: A heterogeneity laminating bipolar transistor and a formation method thereof are provided to reduce a parasitic capacitance by forming an electrode wiring of an emitter electrode, a base electrode and a collector electrode into an air bridge form using the plating process. CONSTITUTION: A sub-collector pattern(110), a base pattern(120), an emitter pattern(132) and an emitter capping pattern(134) are formed on a substrate. An emitter electrode(136) is formed on the emitter capping pattern. A base electrode(122) is formed on the base pattern. A collector electrode(114) is formed on the sub-collector pattern. The emitter electrode, the base electrode and the collector electrode are exposed by patterning a first dummy pattern. A plating seed layer is formed on the exposed emitter electrode, the base electrode and the collector electrode.
Abstract translation: 目的：提供异质层压双极晶体管及其形成方法，以通过使用电镀工艺将发射电极，基极和集电极的电极布线形成为气桥形式来减小寄生电容。 构成：在基板上形成亚集电体图案（110），基底图案（120），发射极图案（132）和发射极封盖图案（134）。 在发射极盖图案上形成发射电极（136）。 在基底图案上形成基极（122）。 在集电极图案上形成集电极（114）。 通过图案化第一虚拟图案来暴露发射极，基极和集电极。 在暴露的发射极，基极和集电极上形成电镀种子层。
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公开(公告)号：KR100860068B1
公开(公告)日：2008-09-24
申请号：KR1020070043334
申请日：2007-05-04
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: 본 발명은 이종접합 바이폴라 트랜지스터 및 그 제조방법에 관한 것으로서, 본 발명에 의한 이종접합 바이폴라 트랜지스터 제조방법은 (a) 기판 상에 서브 컬렉터층, 컬렉터층, 베이스층, 에미터층 및 에미터캡층을 순차적으로 적층하는 단계; (b) 상기 에미터캡층 상부에 형상반전 리소그라피 방법을 이용하여 역경사를 갖는 감광막을 형성한 후 금속 증착 및 리프트 오프 공정에 의해 에미터 전극을 형성하는 단계; (c) 상기 에미터 전극의 양 측면에 제 1 유전체층을 형성하는 단계; (d) 상기 에미터 전극을 마스크로 하여 상기 에미터캡층 및 상기 에미터층 식각하여 상기 베이스층을 노출시키고 메사형태의 에미터를 형성하는 단계; (e) 상기 제 1 유전체층 및 상기 메사형태의 에미터의 측면에 제 2 유전체층을 형성하는 단계; (f) 상기 에미터 전극을 마스크로 하여 노출된 상기 베이스층의 상부에 상기 에미터 전극과 자기정렬되는 베이스전극을 형성하는 단계를 포함한다.
본 발명에 따르면, 에미터의 옆면에 추가적인 유전체를 사용하여 측벽을 형성함으로써 에미터와 베이스를 분리시키고, 종래의 기술에서 메사형태의 에미터 식각시 불가분하게 발생하는 과도한 하부 식각을 방지할 수 있을 뿐만 아니라 최소의 메사형태의 에미터와 베이스 전극의 간격을 정밀하게 제어할 수 있는 이점이 있다.
이종접합 바이폴라 트랜지스터, 자기정렬, 결정이방성, 메사식각, 에미터전극, 베 이스전극, 이방성식각, 측벽-
Patent Agency Ranking
公开(公告)号：KR100832816B1
公开(公告)日：2008-05-28
申请号：KR1020070050022
申请日：2007-05-23
Applicant: 한국전자통신연구원
IPC: H01L29/70 , H01L29/737
CPC classification number: H01L29/66242 , H01L21/30604 , H01L29/42304
Abstract: A manufacturing method of a hetero junction bipolar transistor is provided to realize self array between emitter-base electrodes by forming a base electrode considering crystal anisotropy without performing an additional process or piling up a separated layer. An emitter cap layer, an emitter layer, a base layer, a primary collector layer(204) and a secondary collector layer(205) are formed on a substrate. An emitter electrode(301) is formed on the emitter cap layer. The base layer is exposed by etching the emitter cap layer and the emitter layer through the anisotropy etching using the emitter electrode as a mask. A base electrode(302) which is self-aligned to the emitter electrode is formed above the exposed base layer. The secondary collector layer is exposed by etching the collector layer and the base layer using the base electrode as the mask. A collector electrode(303) is formed on the secondary collector layer, and the secondary collector layer and the substrate are etched.
Abstract translation: 提供了异质结双极晶体管的制造方法，通过考虑晶体各向异性形成基极，而不进行附加工艺或堆叠分离层，实现发射极 - 基极之间的自阵列。 在基板上形成发射极盖层，发射极层，基极层，初级集电极层（204）和次级集电极层（205）。 发射极电极（301）形成在发射极盖层上。 通过使用发射电极作为掩模，通过各向异性蚀刻蚀刻发射极帽层和发射极层来暴露基底层。 在露出的基底层上形成与发射电极自对准的基极（302）。 通过使用基极作为掩模蚀刻集电体层和基极层来使第二集电体层露出。 集电极（303）形成在二次集电极层上，二次集电极层和基板被蚀刻。
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公开(公告)号：KR1020070061136A
公开(公告)日：2007-06-13
申请号：KR1020060050775
申请日：2006-06-07
Applicant: 한국전자통신연구원
CPC classification number: H01L29/7371 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/66318 , H01L29/7378
Abstract: A hetero-junction bipolar transistor and a method for manufacturing the same are provided to remove an increase of base-collector capacitance by isolating a base pad region from a device region including a base electrode. A hetero-junction bipolar transistor includes a substrate, a collector layer(120), a base layer(130), an emitter layer, a collector electrode(210), a base electrode(180), and an emitter electrode(160). A device region is formed on one side of the substrate and includes a sub-collector layer(110), the collector layer, the base layer, the emitter layer, an emitter cap layer(150), the emitter electrode, and the base electrode. A pad region is formed on the other side of the substrate and includes the sub-collector layer, the collector layer, the base layer, and a base pad. A connective line(200) is used for connecting the base electrode of the device region with the base pad of the pad region in a bridge structure.
Abstract translation: 提供了一种异质结双极晶体管及其制造方法，以通过从包括基极的器件区域隔离基极区域来消除基极集电极电容的增加。 异质结双极晶体管包括基板，集电极层（120），基极层（130），发射极层，集电极（210），基极（180）和发射极（160）。 器件区域形成在衬底的一侧上，并且包括副集电极层（110），集电极层，基极层，发射极层，发射极帽层（150），发射极电极和基极 。 衬底区域形成在衬底的另一侧，并且包括副集电极层，集电极层，基极层和基座。 连接线（200）用于将装置区域的基极与衬垫区域的基座焊接在桥结构中。
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公开(公告)号：KR100518451B1
公开(公告)日：2005-09-30
申请号：KR1020030085822
申请日：2003-11-28
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: 절연막 리프트-오프(lift-off)를 활용한 이종접합 쌍극자 트랜지스터(Heterojunction Bipolar Transistor : HBT) 마이크로웨이브 단일기판 집적회로(Monolithic Microwave Integrated Circuit : MMIC) 제작방법을 제시한다. 본 발명에서는 HBT MMIC의 제작에서 필수적인 비아(via)를 형성하기 위하여 형상반전패턴인 포토레지스트 패턴을 형성한 후, 양질의 절연막을 저온에서 증착한다. 그런 다음, 포토레지스트 패턴과 절연막을 동시에 리프트-오프하여 비아를 개방한다. 이렇게 함으로써, 고온의 절연막 증착 공정과 절연막 식각 공정으로 비아를 형성하던 종래에 비하여 전류이득 감소를 최소화할 수 있다.
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公开(公告)号：KR1020040017698A
公开(公告)日：2004-02-27
申请号：KR1020020050124
申请日：2002-08-23
Applicant: 한국전자통신연구원
IPC: C25D7/12
Abstract: PURPOSE: An electroplating device is provided which further improves uniformity of plating thickness by changing a member for resting an object to be plated into an electrode ring and constructing the electrode ring in an inclined shape so that bubbles generated from the surface of wafer that is the object to be plated are easily removed. CONSTITUTION: The electroplating device comprises a plating pot(100) which forms an external appearance, and in which a plating solution is contained; a metal box(110) positioned inside the plating pot and formed of the same metal as plating metal; an inclined electrode ring(120) which is positioned oppositely to the metal box in the plating pot, and on which an object to be plated is rested; a metal box fixing frame(140) for fixing the metal box; an electrode ring fixing frame(130) for fixing the inclined electrode ring; and power supply terminals(150,160) connected to the metal box and inclined electrode ring, wherein a wafer holder(170) is attached to the inclined electrode ring so that a wafer i.e., the object to be plated is rested on the wafer holder, wherein a chemical resistant material such as Teflon and polyethylene is coated on the surface of the metal box fixing frame and electrode ring fixing frame, and wherein the power supply terminals are connected to the metal box and inclined electrode ring through an inner part of the metal box fixing frame and electrode ring fixing frame.
Abstract translation: 目的：提供一种电镀装置，其通过改变用于将要镀覆的物体放置在电极环中并将该电极环形成为倾斜形状的构件，从而进一步提高电镀厚度的均匀性，使得从晶片的表面产生的气泡为 被镀物体很容易去除。 构成：电镀装置包括形成外观的电镀罐（100），其中包含电镀液; 金属盒（110），其位于所述电镀槽内并由与所述电镀金属相同的金属形成; 倾斜电极环（120），与电镀锅中的金属盒相对地定位，待镀物体放置在该倾斜电极环上; 金属盒固定框架（140），用于固定金属盒; 用于固定所述倾斜电极环的电极环固定框架（130）; 以及连接到金属盒和倾斜电极环的电源端子（150,160），其中晶片保持器（170）附接到倾斜电极环，使得晶片（即被电镀物体）搁置在晶片保持器上，其中 在金属盒固定框架和电极环固定框架的表面上涂覆了特氟龙和聚乙烯等耐化学性材料，其中电源端子通过金属盒的内部连接到金属盒和倾斜电极环 固定框架和电极环固定架。
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公开(公告)号：KR1020030027313A
公开(公告)日：2003-04-07
申请号：KR1020010060457
申请日：2001-09-28
Applicant: 한국전자통신연구원
IPC: H01L21/331
Abstract: PURPOSE: A method for fabricating a heterojunction bipolar transistor is provided to improve planarization and integration, by defining an isolation region through a selective ion implantation process, by growing a base layer and an emitter layer while using a dielectric layer as a mask and by simultaneously forming an emitter electrode, a base ohmic electrode and a collector ohmic electrode. CONSTITUTION: The isolation region(103) is defined in a semi-insulating compound semiconductor substrate(101). A sub collector layer(104) and a collector layer(105) are continuously grown on the compound semiconductor substrate. The collector layer is etched to define an intrinsic base region(106). The first dielectric layer is formed on a side surface and an upper surface of the collector layer. A base region is formed on the collector layer. The second dielectric layer is formed on the base layer(108) to expose the intrinsic base region. The emitter layer(110) and an emitter cap layer(111) are formed on the exposed base region. The first dielectric layer and the collector layer are etched to form an open region(112) for a collector electrode. A primary collector electrode(113) is formed in the open region for the collector electrode. The second dielectric layer is etched to expose an outer base region of the base region so that an open region(114) for a base electrode is formed. The emitter electrode(115), the base electrode(116) and a secondary collector electrode(117) are simultaneously formed on the emitter cap layer, the open region for the base electrode and the primary collector electrode.
Abstract translation: 目的：提供一种用于制造异质结双极晶体管的方法，通过在使用电介质层作为掩模的同时生长基底层和发射极层，通过选择性离子注入工艺限定隔离区域，从而改善平面化和整合 形成发射电极，基极欧姆电极和集电极欧姆电极。 构成：隔离区域（103）被限定在半绝缘化合物半导体衬底（101）中。 在化合物半导体衬底上连续生长副集电极层（104）和集电极层（105）。 蚀刻集电极层以限定本征基极区域（106）。 第一电介质层形成在集电体层的侧表面和上表面上。 在集电体层上形成基极区域。 第二电介质层形成在基底层（108）上以露出本征基极区域。 发射极层（110）和发射极盖层（111）形成在暴露的基极区域上。 蚀刻第一电介质层和集电极层以形成用于集电极电极的开放区域（112）。 在集电极的开放区域形成有集电极（113）。 蚀刻第二电介质层以暴露基极区域的外部基极区域，从而形成用于基底电极的开放区域（114）。 发射极电极（115），基极（116）和次级集电极（117）同时形成在发射极盖层，基极开路区域和初级集电极电极上。
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