公开(公告)号：KR1020030002416A

公开(公告)日：2003-01-09

申请号：KR1020010038011

申请日：2001-06-29

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  장재홍 ,  김충기 ,  박문양 ,  김성도 ,  윤용식 ,  박필재 ,  김남수 ,  김천수 ,  황남 ,  박정우

IPC: H01L27/04

Abstract: PURPOSE: A multi-metal inductor is provided to reduce a loss of a substrate and minimize a loss of a serial resistance generated from an inductor line by controlling the width of metal wires. CONSTITUTION: The first insulating layer(20) of TEOS/BPSG is formed on a silicon substrate(10). The second insulating layer(40) having a structure of SiO2/SOG/SiO2 is formed on the first insulating layer(20). The first metal wire(30) is formed on the second insulating layer(40). A via-hole(50) is formed on the second insulating layer(40) in order to connect the second metal wire(60) for forming the first metal wire(30) and the inductor. The third insulating layer(80) having the structure of SiO2/SOG/SiO2 is formed on the second insulating layer(40). A plurality of metal layers are formed within the third insulating layer(60). The third metal wire(70) is formed on the second metal wire(60). The third metal wire(70) is protected by a protective layer(90). The third metal wire(70) is connected with the second metal wire(60) through a via hole(51).

Abstract translation: 目的：提供多金属电感以减少基板的损耗，并通过控制金属线的宽度来最小化从电感线产生的串联电阻的损失。 构成：TEOS / BPSG的第一绝缘层（20）形成在硅衬底（10）上。 在第一绝缘层（20）上形成具有SiO 2 / SOG / SiO 2结构的第二绝缘层（40）。 第一金属线（30）形成在第二绝缘层（40）上。 为了连接用于形成第一金属线（30）的第二金属线（60）和电感器，在第二绝缘层（40）上形成通孔（50）。 具有SiO 2 / SOG / SiO 2结构的第三绝缘层（80）形成在第二绝缘层（40）上。 在第三绝缘层（60）内形成多个金属层。 第三金属线（70）形成在第二金属线（60）上。 第三金属线（70）由保护层（90）保护。 第三金属线（70）通过通孔（51）与第二金属线（60）连接。

公开(公告)号：KR1020020035193A

公开(公告)日：2002-05-11

申请号：KR1020000065358

申请日：2000-11-04

Applicant: 한국전자통신연구원

Inventor： 김천수 ,  유현규 ,  황남 ,  박정우

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A high frequency power device is provided to simplify a fabricating process, by doping impurities to a trench formed in a source region and by filling polysilicon so that an ion implantation process and a high-temperature diffusion process necessitating high energy become unnecessary. CONSTITUTION: A semiconductor layer is of the first conductivity type. A field region of a trench structure is formed in a side of the semiconductor layer. A gate electrode(44) is formed on a predetermined surface of the semiconductor layer. A channel layer(46) of the second conductivity type is laterally diffused from the field region to a width including both sides of the gate electrode and is formed on the semiconductor layer. A source region(47) of the second conductivity type is formed in the channel layer between one side of the gate electrode and the field region. A drain region(48) of the second conductivity type is formed on the semiconductor layer, having a predetermined interval at the other side of the gate electrode. A sinker(37) of the first conductivity type is connected to the semiconductor layer, having a pillar type of a trench structure which penetrates the source region and forms two source regions. A lightly-doped-drain(LDD) region(45) of the second conductivity type is formed on the semiconductor substrate between the drain region and the gate electrode. The first metal electrode is electrically connected to the semiconductor layer through the sinker, in contact with the source regions. The second metal electrode comes in contact with the drain region.

Abstract translation: 目的：提供高频功率器件，以简化制造工艺，通过将杂质掺杂到在源极区域中形成的沟槽并且通过填充多晶硅，使得不需要离子注入工艺和需要高能量的高温扩散工艺。 构成：半导体层是第一导电类型。 沟槽结构的场区形成在半导体层的一侧。 在半导体层的预定表面上形成栅电极（44）。 第二导电类型的沟道层（46）从场区横向扩散到包括栅电极的两侧的宽度，并形成在半导体层上。 在栅电极的一侧和场区之间的沟道层中形成第二导电类型的源极区（47）。 第二导电类型的漏区（48）形成在半导体层上，在栅电极的另一侧具有预定间隔。 第一导电类型的沉降片（37）连接到具有贯穿源极区域并形成两个源极区域的沟槽结构的柱状的半导体层。 在漏区和栅电极之间的半导体衬底上形成第二导电类型的轻掺杂漏极（LDD）区（45）。 第一金属电极通过沉降片与半导体层电连接，与源极区域接触。 第二金属电极与漏极区域接触。