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公开(公告)号：KR1020040055085A
公开(公告)日：2004-06-26
申请号：KR1020020081680
申请日：2002-12-20
Applicant: 한국전자통신연구원
IPC: H03L7/097
Abstract: PURPOSE: A frequency synthesizer for multi-band and a method for synthesizing a frequency are provided to process the multi-band under the low power by using a VCO(Voltage Controlled Oscillator). CONSTITUTION: A frequency/phase detector(200) compares a reference frequency with a feedback frequency and outputs a compared result. A charge pump circuit(300) converts the compared result to the current. A low pass filter(400) generates a voltage corresponding to the output current of the charge pump circuit. A VCO(500) outputs a voltage controlled frequency corresponding to an output voltage of the low pass filter. A division circuit(600) divides the voltage controlled frequency of the VCO by a band selection ratio and outputs a desired band frequency. A channel selection division circuit(700) divides the band frequency by a channel selection ratio and generates the feedback frequency.
Abstract translation: 目的：提供用于多频带的频率合成器和用于合成频率的方法，以通过使用VCO（压控振荡器）在低功率下处理多频带。 构成：频率/相位检测器（200）将参考频率与反馈频率进行比较，并输出比较结果。 电荷泵电路（300）将比较结果转换成电流。 低通滤波器（400）产生对应于电荷泵电路的输出电流的电压。 VCO（500）输出对应于低通滤波器的输出电压的电压控制频率。 分频电路（600）将VCO的压控频率除以频带选择比，并输出期望的频带频率。 频道选择分频电路（700）将频带频率除以频道选择比，并产生反馈频率。
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公开(公告)号：KR1020040055084A
公开(公告)日：2004-06-26
申请号：KR1020020081679
申请日：2002-12-20
Applicant: 한국전자통신연구원
IPC: H03L7/08
Abstract: PURPOSE: A frequency synthesizer for detecting current of a charge pump circuit is provided to minimize a delay time of a delay signal for resetting a frequency/phase detector by predicting accurately the variation according to various conditions. CONSTITUTION: A frequency synthesizer for detecting current of a charge pump circuit includes a frequency/phase detector, a charge pump circuit, and a current detector. The frequency/phase detector(100) is used for receiving the first frequency and outputting the first and the second control signals corresponding the first frequency. The charge pump circuit(200) is used for outputting the first current and the second current in response to the first and the second control signals. The current detector(300) is used for detecting a period when the first current and second current flow simultaneously, and outputting a delay signal for resetting the frequency/phase detector.
Abstract translation: 目的：提供一种用于检测电荷泵电路电流的频率合成器，用于通过根据各种条件准确地预测变化来最小化用于复位频率/相位检测器的延迟信号的延迟时间。 构成：用于检测电荷泵电路的电流的频率合成器包括频率/相位检测器，电荷泵电路和电流检测器。 频率/相位检测器（100）用于接收第一频率并输出对应于第一频率的第一和第二控制信号。 电荷泵电路（200）用于响应于第一和第二控制信号输出第一电流和第二电流。 电流检测器（300）用于同时检测第一电流和第二电流的周期，并且输出用于复位频率/相位检测器的延迟信号。
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公开(公告)号：KR1020030055758A
公开(公告)日：2003-07-04
申请号：KR1020010085836
申请日：2001-12-27
Applicant: 한국전자통신연구원
IPC: H03G3/00
CPC classification number: H03G1/0017 , H03F3/45197 , H03F2203/45504 , H03F2203/45726 , H03G1/007 , H03G7/00
Abstract: PURPOSE: A variable gain amplification circuit of an automatic gain control is provided, which achieves a pseudo exponential function with a simple configuration, and prevents power consumption. CONSTITUTION: A fixed resistor part(R) receives an electric signal, and a variable resistor part(r) is connected to the fixed resistor part serially and has a plurality of NMOS transistors connected in parallel each other by applying different control voltage. The fixed resistor part has the plurality of NMOS transistors operating in a saturated area. The variable resistor part acts as one variable resistor by connecting the plurality of NMOS transistors in parallel operating in a linear area.
Abstract translation: 目的：提供自动增益控制的可变增益放大电路，通过简单的配置实现伪指数函数，防止功耗。 构成：固定电阻器部分（R）接收电信号，并且可变电阻器部分（r）被串联连接到固定电阻器部分，并且通过施加不同的控制电压而具有并联连接的多个NMOS晶体管。 固定电阻部分具有在饱和区域中工作的多个NMOS晶体管。 可变电阻器部分通过在线性区域中并联操作的多个NMOS晶体管而作为一个可变电阻器。
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公开(公告)号：KR1020030013193A
公开(公告)日：2003-02-14
申请号：KR1020010047549
申请日：2001-08-07
Applicant: 한국전자통신연구원
IPC: H03D7/00
CPC classification number: H03D7/1441 , H03D7/1408 , H03D7/1458 , H03D7/1466 , H03D7/1475
Abstract: PURPOSE: A frequency mixer using half local oscillation frequency is provided to remove an offset of a direct current voltage when using a frequency mixer at a homo heterodyne transceiver, and to half a frequency of a local oscillator needed for a high frequency heterodyne transceiver. CONSTITUTION: The first and second input terminals(IN+,IN-) receive high frequency signals as differential signals. The first mixing part(100) comprises the first and second NMOS transistors(M10,M20), which have sources connected to the first input terminal(IN+), drains connected to each other, and gates connected to receive signals(LO+,LO-) from a local oscillator. The second mixing part(200) comprises the third and fourth NMOS transistors(M30,M40), which have sources connected to the second input terminal(IN-), drains connected to each other, and gates connected to receive the signals(LO+,LO-) from the local oscillator.
Abstract translation: 目的：提供使用半本地振荡频率的混频器，以在同频外差收发器使用混频器时消除直流电压的偏移，以及高频外差收发器所需的本地振荡器的一半频率。 构成：第一和第二输入端子（IN +，IN-）接收高频信号作为差分信号。 第一混合部分（100）包括第一和第二NMOS晶体管（M10，M20），其具有连接到第一输入端（IN +）的源极，彼此连接的漏极，以及连接到接收信号（LO +，LO- ）从本地振荡器。 第二混合部分（200）包括具有连接到第二输入端子（IN-）的源极的第三和第四NMOS晶体管（M30，M40），彼此连接的漏极，以及连接以接收信号（LO +， LO-）。
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公开(公告)号：KR1020030002416A
公开(公告)日：2003-01-09
申请号：KR1020010038011
申请日：2001-06-29
Applicant: 한국전자통신연구원
IPC: H01L27/04
Abstract: PURPOSE: A multi-metal inductor is provided to reduce a loss of a substrate and minimize a loss of a serial resistance generated from an inductor line by controlling the width of metal wires. CONSTITUTION: The first insulating layer(20) of TEOS/BPSG is formed on a silicon substrate(10). The second insulating layer(40) having a structure of SiO2/SOG/SiO2 is formed on the first insulating layer(20). The first metal wire(30) is formed on the second insulating layer(40). A via-hole(50) is formed on the second insulating layer(40) in order to connect the second metal wire(60) for forming the first metal wire(30) and the inductor. The third insulating layer(80) having the structure of SiO2/SOG/SiO2 is formed on the second insulating layer(40). A plurality of metal layers are formed within the third insulating layer(60). The third metal wire(70) is formed on the second metal wire(60). The third metal wire(70) is protected by a protective layer(90). The third metal wire(70) is connected with the second metal wire(60) through a via hole(51).
Abstract translation: 目的：提供多金属电感以减少基板的损耗，并通过控制金属线的宽度来最小化从电感线产生的串联电阻的损失。 构成：TEOS / BPSG的第一绝缘层（20）形成在硅衬底（10）上。 在第一绝缘层（20）上形成具有SiO 2 / SOG / SiO 2结构的第二绝缘层（40）。 第一金属线（30）形成在第二绝缘层（40）上。 为了连接用于形成第一金属线（30）的第二金属线（60）和电感器，在第二绝缘层（40）上形成通孔（50）。 具有SiO 2 / SOG / SiO 2结构的第三绝缘层（80）形成在第二绝缘层（40）上。 在第三绝缘层（60）内形成多个金属层。 第三金属线（70）形成在第二金属线（60）上。 第三金属线（70）由保护层（90）保护。 第三金属线（70）通过通孔（51）与第二金属线（60）连接。
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Patent Agency Ranking
公开(公告)号：KR100501901B1
公开(公告)日：2005-07-25
申请号：KR1020020083234
申请日：2002-12-24
Applicant: 한국전자통신연구원
IPC: H03G3/00
Abstract: 본 발명의 가변 이득 증폭기는, 이득 특성은 지수함수 특성을 갖고, 증폭기의 이득이 입력 제어 전압에 따라 연속적으로 가변하는 특성을 갖도록 하며, 회로의 단순화를 통한 저면적화와, 회로의 구조적 개선을 통한 고 선형성 및 저잡음화의 특성을 얻을 수 있는 가변 이득 증폭기를 제공하는데 그 목적이 있다.
상기 목적을 달성하기 위하여 본 발명은, 외부 제어 전압을 인가받고, 상기 외부 제어 전압을 변환한 후, 복수개의 단계로 분배하며, 분배된 복수개의 단계 전압을 복수개의 내부 제어 신호로서 출력하는 제어 신호 발생부; 상기 복수개의 내부 제어 신호를 입력받고, 상기 복수개의 내부 제어 신호에 따라 가변적인 저항값을 제공하는 가변저항부; 및 W/L이 서로 다른 병렬 쌍 결합 차동 증폭기를 내부에 구비하고, 상기 가변저항부가 제공하는 저항값에 따라 비반전 신호 및 반전 신호의 차동 성분을 증폭하는 차동 증폭부를 포함한다.-
公开(公告)号：KR1020040054439A
公开(公告)日：2004-06-25
申请号：KR1020020081477
申请日：2002-12-18
Applicant: 한국전자통신연구원
IPC: H03K3/027
CPC classification number: H03K3/356104 , H03K3/012 , H03K23/667
Abstract: PURPOSE: A flipflop using complementary clocking and a prescaler using the same are provided to improve the current driving capacity by using the complementary relation between an NMOS transistor and a PMOS transistor. CONSTITUTION: A first p-type transistor(mp11) is connected between a supply voltage supply unit and the first node to receive data. A second p-type transistor(mp12) is connected between the first and the second nodes to receive the first clock. A first n-type transistor(mn11) is connected between the second node and the ground to receive the data. A third p-type transistor(mp13) is connected between the supply voltage supply unit and the third node. A second n-type transistor(mn12) is connected between the third and the fourth nodes to receive the first clock. A third n-type transistor(mn13) is connected between the fourth node and the ground. A fourth p-type transistor(mp14) is connected between the supply voltage supply unit and an output terminal. A fourth n-type transistor(mn14) is connected between the output terminal and the ground to receive the second clock. A fifth n-type transistor is connected between the first and the second nodes to receive the second clock. A fifth p-type transistor is connected between the third and the fourth nodes to receive the second clock.
Abstract translation: 目的：提供使用互补时钟的触发器和使用其的预分频器，以通过使用NMOS晶体管和PMOS晶体管之间的互补关系来提高电流驱动能力。 构成：第一个p型晶体管（mp11）连接在电源电压单元和第一个节点之间以接收数据。 第二p型晶体管（mp12）连接在第一和第二节点之间以接收第一时钟。 第一n型晶体管（mn11）连接在第二节点和地之间以接收数据。 第三p型晶体管（mp13）连接在电源电压单元和第三节点之间。 第二n型晶体管（mn12）连接在第三和第四节点之间以接收第一时钟。 第三n型晶体管（mn13）连接在第四节点和地之间。 第四个P型晶体管（mp14）连接在电源电压单元和输出端子之间。 第四n型晶体管（mn14）连接在输出端和地之间以接收第二时钟。 第五n型晶体管连接在第一和第二节点之间以接收第二时钟。 第五个p型晶体管连接在第三和第四个节点之间以接收第二个时钟。
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公开(公告)号：KR100421417B1
公开(公告)日：2004-03-09
申请号：KR1020010065150
申请日：2001-10-22
IPC: H03F1/42
Abstract: PURPOSE: A broadband high gain amplification circuit is provided to maintain a high gain and a bandwidth even though an input frequency is increased. CONSTITUTION: An amplification part(100) amplifies an input signal. An impedance control part(200) constitutes a current mirror by receiving a constant voltage(Vb1), and improves a gain of the amplification part by increasing an output impedance of the amplification part at a half power frequency where the gain of the amplification becomes a half of its peak value. The impedance control part includes an inductor(210) connected to a power supply, and a PMOS(220) having a gate connected to the constant voltage and being connected to the inductor, and a resistor(230) connected between one side of the PMOS and another side of the inductor and connected to another side of the PMOS.
Abstract translation: 目的：提供宽带高增益放大电路以保持高增益和带宽，即使输入频率增加。 构成：放大部分（100）放大输入信号。 通过接收恒定电压（Vb1），阻抗控制部（200）构成电流反射镜，并且通过在放大部的增益变为α的半功率频率处增大放大部的输出阻抗来提高放大部的增益 其峰值的一半。 阻抗控制部分包括连接到电源的电感器（210）和具有连接到恒定电压的栅极并连接到电感器的PMOS（220），以及连接在PMOS的一侧之间的电阻器（230） 并且电感器的另一侧连接到PMOS的另一侧。
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公开(公告)号：KR100413182B1
公开(公告)日：2003-12-31
申请号：KR1020010075186
申请日：2001-11-30
Applicant: 한국전자통신연구원
IPC: H03F3/45
CPC classification number: H03G1/007 , H03F3/45179 , H03F2203/45492 , H03G1/0023
Abstract: An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
Abstract translation: 公开了一种使用可变负反馈电阻的自动增益可控的线性差分放大器。 线性差分放大器包括输入端，偏置电流源，负载单元，第一MOS晶体管和第二MOS晶体管。 本发明的线性差分放大器可以根据输入信号控制放大增益并且改善线性度IIP3，而不需要由增加线性度引起的额外功耗。自动增益可控的线性差分放大器使用NMOS / PMOS晶体管， 放大器可以更加方便和高效地实现。
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公开(公告)号：KR1020030044444A
公开(公告)日：2003-06-09
申请号：KR1020010075186
申请日：2001-11-30
Applicant: 한국전자통신연구원
IPC: H03F3/45
CPC classification number: H03G1/007 , H03F3/45179 , H03F2203/45492 , H03G1/0023
Abstract: PURPOSE: A differential linear amplifier is provided to improve the linearity(IIP3) viewed from the input side by controlling the gain of the amplification in response to the input signal applied to the differential amplifier as well as improve the IIP3 by utilizing a poly silicon without using the polysilicon as a resistor, thereby obtaining an excellent characteristics. CONSTITUTION: A differential linear amplifier includes an input block for receiving a positive input signal and a negative input signal, a bias current source provided on one side of the input block for supplying a bias current, a pair of load blocks(110,120) provided on the other side of the input block for supplying the different level between the output signals between the positive output terminal and the negative output terminal corresponding to the positive input signal and the negative input signal, a first MOD transistor(210) connected between the bias current source and the input block for utilizing the positive input signal as a gate input and the gain control signal as a substrate bias voltage and a second MOS transistor(220) connected between the bias current source and the input block for utilizing the negative input signal as a gate input and the gain control signal as a substrate bias voltage.
Abstract translation: 目的：提供差分线性放大器，以通过控制放大器的输入信号来响应于差分放大器的输入信号来控制从输入侧观察的线性度（IIP3），并通过利用多晶硅来改善IIP3，而不需要 使用多晶硅作为电阻器，从而获得优异的特性。 构成：差分线性放大器包括用于接收正输入信号和负输入信号的输入块，设置在用于提供偏置电流的输入块的一侧上的偏置电流源，设置在该输入块上的一对加载块（110,120） 用于在与正输入信号和负输入信号相对应的正输出端和负输出端之间的输出信号之间提供不同电平的输入块的另一侧;连接在偏置电流之间的第一MOD晶体管（210） 源极和用于利用正输入信号作为栅极输入和增益控制信号作为衬底偏置电压的输入块和连接在偏置电流源和输入块之间的第二MOS晶体管（220），以将负输入信号用作 栅极输入和增益控制信号作为衬底偏置电压。
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