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    Decimal floating-point quantum exception detection
    101.
    发明专利
    Decimal floating-point quantum exception detection 未知

    公开(公告)号：AU2010353843B2

    公开(公告)日：2014-08-28

    申请号：AU2010353843

    申请日：2010-11-08

    Applicant: IBM

    Inventor： SCHWARZ ERIC MARK ,  YEH PHIL ,  COWLISHAW MICHAEL FREDERIC ,  MUELLER SILVIA MELITTA

    IPC: G06F9/302 ,  G06F7/491 ,  G06F7/499 ,  G06F9/38

    Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.

    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT
    102.
    发明专利
    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT 未知

    公开(公告)号：CA2852862A1

    公开(公告)日：2013-07-04

    申请号：CA2852862

    申请日：2012-11-13

    Applicant: IBM

    Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  MITRAN MARCEL ,  COPELAND REID

    IPC: G06F9/30 ,  G06F9/318

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

    Residue calculation in modulo system using 4:2 counter
    103.
    发明专利
    Residue calculation in modulo system using 4:2 counter 未知

    公开(公告)号：GB2456406A

    公开(公告)日：2009-07-22

    申请号：GB0822762

    申请日：2008-12-15

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  FLEISCHER BRUCE MARTIN ,  HAESS JUERGEN ,  TRONG SON DAO ,  SCHWARZ ERIC MARK ,  WETTER HOLGER

    IPC: G06F7/72

    Abstract: A residue of an operand with a width of n bits with respect to a modulo m where m=2b-1, can be calculated by partitioning the operand into segments, each of b bits starting with the Least Significant Bit (LSB). The segments are applied to a counter reduction tree (21) comprising levels (22, 23) of adders (24) The adders (24) of a first level (22) below an operand register (25) with successive registers keeping the successive bit positions of the operand are 4:2 counters (24) having four inputs (In1, In2, In3, In4) plus a propagate input (44), a carry and a sum output (45, 46) plus a propagate output (43) each. the first level (22) are grouped in fours, such that the propagate outputs (43) are ring like connected with the propagate inputs (44), and that the first to fourth inputs (In1, In2, In3, In4) of the counters (24) are connected with successive registers of said operand register (25) such that first inputs (In4) of the counters (24) are connected with four successive registers in ascending order followed by second (In3), third (In2) and fourth inputs (In1), wherein a decoding is performed only one time at the end of the counter tree (21) and thus at the end of the residue generation process. This leads to a reduction in the area needed on the chip to make the calculation, relaxes the timing requirement, as the calculation requires fewer logical levels, and increases the error detection rate for a single random type of operation.

    Method for executing a load instruction in a pipeline processor, putting the data in the target address into a buffer then loading the requested data.
    104.
    发明专利
    Method for executing a load instruction in a pipeline processor, putting the data in the target address into a buffer then loading the requested data. 未知

    公开(公告)号：GB2454816A

    公开(公告)日：2009-05-20

    申请号：GB0822115

    申请日：2008-12-04

    Applicant: IBM

    Inventor： TRONG SON DAO ,  HAESS JUERGEN ,  HUTTON DAVID SHANE ,  KLEIN MICHAEL ,  RELL JOHN GILBERT JR ,  SCHWARZ ERIC MARK ,  SHUM KEVIN CHUNG-LUNG

    IPC: G06F9/312 ,  G06F9/38

    Abstract: Disclosed is a method and system for operating the execution unit of a computer, the execution unit having a pipeline-based execution flow during which load instructions are processed. The load instructions having the function of loading data from a storage means into a predetermined location within the pipeline, preferably a register-implemented pipeline. The method has the steps of, when a load instruction occurs in the pipeline, reading (610) the current value of the target location, and buffering (620) the current target value at a predetermined location within said pipeline. Next, the value of the source location is loaded (610) and stored (620) at the target location, the pipeline is executed according to its execution flow, using the loaded value for computing purposes. If an event (630) indicating that the loaded value is not correct occurs, (660) the buffered original value may be used instead of the loaded value. The execution unit may be a floating point unit with the reading and/or loading of the data being done using a multiply-add data path.

    Vector string search instruction
    106.
    发明专利
    Vector string search instruction 未知

    公开(公告)号：AU2020221962A1

    公开(公告)日：2021-06-03

    申请号：AU2020221962

    申请日：2020-02-11

    Applicant: IBM

    Inventor： LICHTENAU CEDRIC ,  BRADBURY JONATHAN ,  SCHWARZ ERIC MARK ,  FIGULI RAZVAN PETER ,  PAYER STEFAN

    IPC: G06F16/903

    Abstract: An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

    VECTOR EXCEPTION CODE
    107.
    发明专利
    VECTOR EXCEPTION CODE 未知

    公开(公告)号：CA2895653C

    公开(公告)日：2020-08-04

    申请号：CA2895653

    申请日：2013-12-06

    Applicant: IBM

    Inventor： BRADBURY JONATHAN DAVID ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GSCHWIND MICHAEL KARL

    IPC: G06F17/16

    Abstract: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.

    INSTRUCCIÓN DE SUMA DE COMPROBACIÓN DEL VECTOR.
    109.
    发明专利
    INSTRUCCIÓN DE SUMA DE COMPROBACIÓN DEL VECTOR. 未知

    公开(公告)号：MX344922B

    公开(公告)日：2017-01-11

    申请号：MX2015009457

    申请日：2013-12-04

    Applicant: IBM

    Inventor： SCHWARZ ERIC MARK ,  BRADBURY JONATHAN DAVID

    IPC: G06F9/30

    Abstract: Una instrucción de la Suma de Comprobación del Vector. Los elementos de un segundo operando se suman uno por uno para obtener un primer resultado. La suma incluye realizar una o más operaciones de suma con acarreo de redondeo final. El primer resultado se coloca en un elemento de un primer operando de la instrucción. Después de cada adición de un elemento, un acarreo de una posición elegida de la suma, si lo hay, se suma a una posición seleccionada en un elemento del primer operando.

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