公开(公告)号：IT1319493B1

公开(公告)日：2003-10-20

申请号：ITMI20002593

申请日：2000-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI

IPC: G06F20060101

公开(公告)号：DE69629669D1

公开(公告)日：2003-10-02

申请号：DE69629669

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO ,  MACCARRONE MARCO

IPC: G11C16/28 ,  G11C16/06

Abstract: The read circuit presents a current mirror circuit (9) including a first and second load transistor (12, 13) interposed between the supply line (15) and a respective first and second output node (16, 17); the first output node (16) is connected to a cell (4) to be read; the second output node (17) is connected to a generating stage (20, 51) generating a reference current (IR1) having a predetermined characteristic; and the size of the second load transistor (13) is N times greater than the first load transistor (12). To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit (55) presents a current balancing branch (75) connected between the first output node (16) and ground for generating an equalizing current (IB) presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

公开(公告)号：DE69524572T2

公开(公告)日：2002-08-22

申请号：DE69524572

申请日：1995-04-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28

Abstract: A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means (1) for converting a current of a memory cell (MC) to be read into a voltage signal (V9), second current voltage/conversion means (2) for converting a reference current into a reference voltage signal (V20), and voltage comparator means (3) for comparing the voltage signal (V9) with the reference voltage signal (V20); the sense amplifier circuit comprises capacitive decoupling means (C1) for decoupling the voltage signal (V9) from the comparator means (3), and means (13) for providing the capacitive decoupling means (C1) with an electric charge suitable for compensating an offset voltage introduced in the voltage signal (V9) by an offset current superimposed on the current of the memory cell (MC) to be read.

公开(公告)号：DE69514502T2

公开(公告)日：2000-08-03

申请号：DE69514502

申请日：1995-05-05

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  CAMPARDO GIOVANNI ,  FUSILLO GIUSEPPE ,  SILVAGNI ANDREA

IPC: G11C8/12 ,  G11C16/08 ,  G11C11/00 ,  G11C8/00

Abstract: A memory array (2) is divided, at the design stage, into a plurality of elementary sectors (4); depending on the specific application and the requirements of the user, the elementary sectors are grouped into composite sectors (34) of desired size and number; a correlating unit (31) memorizes the correlation between each composite sector and the elementary sectors; and, to address a composite sector, the relative address (32) is supplied to the correlating unit (31) which provides for addressing the elementary sectors (4) associated with the addressed composite sector on the basis of the memorized correlation table.

公开(公告)号：ITTO980497A1

公开(公告)日：1999-12-06

申请号：ITTO980497

申请日：1998-06-05

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

IPC: G11C8/10

Abstract: A decoder comprises a first line placed at a first reference potential (VCC); a second line placed at a second reference potential switchable between the first reference potential and at least one programming potential higher than the first reference potential; a voltage elevator circuit connected to the second line, receiving a control signal and generating at an output a third reference potential switchable, on the basis of the control signal, between the first reference potential, the programming potential and a boosted potential which is between the first reference potential and the reference potential; a third line connected to the output of the voltage elevator circuit; an input circuit connected to the first line and receiving a predecoding signal, an output biasing circuit connected to said third line and generating a biasing signal for one line of the memory device; and switch circuit located between the input circuit and the biasing circuit, receiving a driving signal for selectively breaking the electrical connection between the input circuit and the biasing circuit on the basis of the driving signal.

公开(公告)号：DE69325443D1

公开(公告)日：1999-07-29

申请号：DE69325443

申请日：1993-03-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

Abstract: To reduce the read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. In this way, the threshold voltage of the above cells (the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to the "body effect", whereby the threshold voltage depends, among other things, on the voltage drop between the cell terminal operating as the source and the substrate, and increases alongside an increase in the voltage drop.