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    NON-VOLATILE MEMORY HAVING BURST MODE READING FUNCTION AND PAGE MODE READING FUNCTION DURING INTERRUPTION PERIOD OF ELECTRIC CHANGE OPERATION
    1.
    发明专利
    NON-VOLATILE MEMORY HAVING BURST MODE READING FUNCTION AND PAGE MODE READING FUNCTION DURING INTERRUPTION PERIOD OF ELECTRIC CHANGE OPERATION 失效

    公开(公告)号：JP2001057087A

    公开(公告)日：2001-02-27

    申请号：JP2000227222

    申请日：2000-07-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARTOLI SIMONE ,  BEDARIDA LORENZO ,  SALI MAURO ,  RUSSO ANTONIO

    IPC: G11C16/02

    Abstract: PROBLEM TO BE SOLVED: To obtain a memory having a burst mode reading function and a page mode reading function while erasing or programming one sector in a semiconductor memory having two or more memory sectors S1-S9. SOLUTION: This semiconductor memory is provided with first control circuit means 4, 6 for controlling the electrical change operation of contents of a memory. The first control circuit means 4 (6) can execute selectively the operation for changing electrically one content of a memory sector and can interrupt the execution so as to be possible to reading-access the other memory sectors. The memory is characterized by providing second control circuit means 8, 6 which can permit burst mode reading or page mode reading operation for reading contents of the other memory sectors.

    2.
    发明专利
    未知

    公开(公告)号：DE69940369D1

    公开(公告)日：2009-03-19

    申请号：DE69940369

    申请日：1999-11-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARTOLI SIMONE ,  GERACI ANTONINO ,  SALI MAURO ,  BEDARIDA LORENZO

    IPC: G11C7/00 ,  G11C7/10

    Abstract: The invention relates to a read control circuit portion (1) and an attendant reading method for an electronic memory device (2) integrated in a semiconductor and including a non-volatile memory matrix (4) with associated row and column decoders (5,6) connected to respective outputs of an address counter (7), an ATD circuit (12) for detecting an input transaction as the memory device is being accessed, and read amplifiers (8) and attendant registers (10) for transferring the data read from the memory (2) to the output. The control circuit portion (1) comprises a detection circuit block (15) which is input a clock signal (CK) and a logic signal (BAN) to enable reading in the burst mode, and a burst read mode control logic (3) connected downstream of the circuit block (15). The method of this invention comprises accessing the memory matrix in a random read mode; detecting a request for access in the burst read mode; and executing the parallel reading of a plurality of memory words during a single period of time clocked by a clock signal (CK).

    8.
    发明专利
    未知

    公开(公告)号：ITMI20001315A1

    公开(公告)日：2001-12-13

    申请号：ITMI20001315

    申请日：2000-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  GERACI ANTONINO ,  LISI CARLO ,  DIMA VINCENZO

    IPC: G11C16/28

    Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

    10.
    发明专利
    未知

    公开(公告)号：ITMI992487D0

    公开(公告)日：1999-11-26

    申请号：ITMI992487

    申请日：1999-11-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  BETTINI LUIGI

    IPC: G11C7/06 ,  G11C7/22 ,  H03K3/011 ,  H03K3/355 ,  H03K5/04

    Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.

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