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    102.
    发明专利
    未知

    公开(公告)号：ITVA910026D0

    公开(公告)日：1991-08-30

    申请号：ITVA910026

    申请日：1991-08-30

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22

    Abstract: A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.

    107.
    发明专利
    未知

    公开(公告)号：DE60141200D1

    公开(公告)日：2010-03-18

    申请号：DE60141200

    申请日：2001-05-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C16/04 ,  G11C16/26

    Abstract: A memory system (1000) comprises a memory matrix (110) formed on a semiconductor structure, the memory matrix including: a first column line (BC-4) and a second column line (BC-5) which are connected electrically to at least one first memory cell (Q65) to be read, for the reading of the at least one first cell (Q65) a first reading voltage can be supplied to the first column line (BC-4), and a third column line (BC-1) distinct from the first column line (BC-4) and from the second column line (BC-5), and is characterized in that it further comprises generating means (SCR) for supplying, to the third column line (BC-1) and during the reading of the at least one first memory cell (Q65), a biasing voltage which can oppose the establishment of an electric current between the first column line (BC-4) and the third column line (BC-1) in the semiconductor structure. The biasing voltage is preferably substantially equal to the first reading voltage.

    108.
    发明专利
    未知

    公开(公告)号：DE602005019069D1

    公开(公告)日：2010-03-11

    申请号：DE602005019069

    申请日：2005-11-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO

    IPC: G11C8/06 ,  G11C16/04 ,  G11C16/08

    Abstract: The invention relates to a method for accessing, in reading, programming and/or erasing, to a semiconductor integrated non volatile memory device of the Flash EEPROM type with a NAND architecture comprising at least one memory matrix (2) organised in rows or word lines (WL) and columns or bit lines (BL), and wherein, for the memory, a plurality of additional address pins are provided. Advantageously, the method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with said additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to said additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

    110.
    发明专利
    未知

    公开(公告)号：DE60226571D1

    公开(公告)日：2008-06-26

    申请号：DE60226571

    申请日：2002-02-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C11/56 ,  G11C16/04 ,  H01L21/28 ,  H01L29/792

    Abstract: An electrically-programmable memory cell programmed by means of injection of channel hot electrons into a charge-storage element (115a,115b;323) capacitively coupled to a memory cell channel (107;307) for modulating a conductivity thereof depending on a stored amount of charge. A first and a second spaced-apart electrode regions (109a,109b;309a,309b) are formed in a semiconductor layer (103;303) and define a channel region (107;307) there between; at least one (109A,109B;309B) of the first and second electrode regions acts as a programming electrode of the memory cell. A control electrode (CG) is capacitively coupled to the charge-storage element. The charge-storage element is placed over the channel to substantially extend from the first to the second electrode regions, and is separated from the channel region by a dielectric layer (1012,113;321). The dielectric layer has a reduced thickness in a portion (113;321b) thereof near the at least one programming electrode.

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