STACKED-DIE MEMS RESONATOR SYSTEM
    107.
    发明申请
    STACKED-DIE MEMS RESONATOR SYSTEM 有权
    堆叠式MEMS谐振器系统

    公开(公告)号:US20170029269A1

    公开(公告)日:2017-02-02

    申请号:US15187748

    申请日:2016-06-20

    Abstract: A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

    Abstract translation: 用于微机电系统(MEMS)谐振器系统的薄型封装结构包括电引线,其具有在封装结构的横截面轮廓内的相应的第一和第二高度处的内部和外部电接触表面,以及模具安装表面 第一和第二高度之间的中间高度。 谐振器控制芯片安装到电引线的管芯安装表面,使得谐振器控制芯片的至少一部分设置在第一和第二高度之间并且引线接合到电气的内部电接触表面 铅。 MEMS谐振器芯片以堆叠的管芯配置安装到谐振器控制芯片,并且电机的谐振器芯片,谐振器控制芯片和内部电接触和管芯安装表面被封装在暴露外部的封装外壳内 电气引线的电接触表面在包装结构的外表面。

    Semiconductor Device and Method for Manufacturing the Same
    108.
    发明申请
    Semiconductor Device and Method for Manufacturing the Same 审中-公开
    半导体装置及其制造方法

    公开(公告)号:US20160355398A1

    公开(公告)日:2016-12-08

    申请号:US14731433

    申请日:2015-06-05

    Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.

    Abstract translation: 本文提供了一种半导体器件。 半导体器件包括:衬底,其包括MEMS区域及其上的连接区域; 设置在所述连接区域中的所述基板上的电介质层; 设置在所述电介质层上的多晶硅层,其中所述多晶硅层用作蚀刻停止层; 设置在所述多晶硅层上的连接焊盘; 以及覆盖所述电介质层的钝化层,其中所述钝化层包括暴露所述连接焊盘的开口和所述连接焊盘与所述钝化层之间的过渡区域。

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