公开(公告)号：US08319108B2

公开(公告)日：2012-11-27

申请号：US12535760

申请日：2009-08-05

Applicant: Atsushi Yamaguchi ,  Koso Matsuno ,  Ryo Kuwabara ,  Hiroe Kowada ,  Kimiaki Nakaya

Inventor： Atsushi Yamaguchi ,  Koso Matsuno ,  Ryo Kuwabara ,  Hiroe Kowada ,  Kimiaki Nakaya

IPC: H05K7/20

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/75 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/0203 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T428/24372 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A mounting structure formed by bonding the electrodes of a substantially planar electronic component to the electrodes provided on the mounting surface of a circuit board includes a sealing body 5 formed between one main surface of the electronic component and the circuit board and/or on the other main surface of the electronic component. The sealing body 5 is composed of a plurality of layers having different adhesive strengths and thermal conductivities, wherein a layer having a relatively high adhesion strength is arranged in a region being in contact with either one of the electronic component and the circuit board, and a layer having a relatively high thermal conductivity is arranged in a region being in contact with none of the electronic component and the circuit board.

Abstract translation: 通过将基本上平面的电子部件的电极接合到设置在电路基板的安装面上的电极而形成的安装结构包括形成在电子部件的一个主面和电路基板之间和/或另一个之间的密封体5 电子元件的主表面。 密封体5由具有不同粘合强度和导热性的多个层组成，其中具有相对较高粘合强度的层被布置在与电子部件和电路板中的任一个接触的区域中，并且 在与电子部件和电路基板没有接触的区域中布置具有较高热传导率的层。

公开(公告)号：US08207452B2

公开(公告)日：2012-06-26

申请号：US12466604

申请日：2009-05-15

Applicant: Issey Yamamoto ,  Akihiko Kamada

Inventor： Issey Yamamoto ,  Akihiko Kamada

IPC: H05K1/11

CPC classification number: H05K1/0271 ,  H05K1/0306 ,  H05K3/12 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0269 ,  H05K2201/09781

Abstract: A multilayer interconnection board includes a plurality of laminated ceramic layers. Wiring electrodes are disposed on principal surfaces of the ceramic layers, and dot patterns are arranged around the wiring electrodes. The dot patterns are arranged such that the density distribution thereof is varied such that the ratio of the presence of the dot patterns in the vicinity of the wiring electrode is relatively large and the ratio of the presence is reduced as the distance from the wiring electrode increases.

Abstract translation: 多层互连板包括多个层压陶瓷层。 布线电极设置在陶瓷层的主表面上，并且点阵图形布置在布线电极周围。 点图案被布置为使得其密度分布变化，使得布线电极附近的点图案的存在比例相对较大，并且随着与布线电极的距离增加而存在的比例降低 。

公开(公告)号：US08198540B2

公开(公告)日：2012-06-12

申请号：US12303513

申请日：2007-06-06

Applicant: Yoshirou Kuromitsu ,  Hiroya Ishizuka ,  Hiroshi Miyata ,  Takeshi Kitahara ,  Hiroshi Tonomura

Inventor： Yoshirou Kuromitsu ,  Hiroya Ishizuka ,  Hiroshi Miyata ,  Takeshi Kitahara ,  Hiroshi Tonomura

IPC: H05K1/00 ,  H05K7/20

CPC classification number: H01L23/3736 ,  H01L23/3735 ,  H01L23/473 ,  H01L24/32 ,  H01L2224/32225 ,  H05K1/09 ,  H05K3/38 ,  H05K2201/0269 ,  Y10T29/49124

Abstract: A power element mounting substrate including a circuit layer brazed to a surface of a ceramic plate, and a power element soldered to a front surface of the circuit layer, wherein the circuit layer is constituted using an Al alloy with an average purity of more than or equal to 98.0 wt % and less than or equal to 99.9 wt %, Fe concentration of the circuit layer at a side of a surface to be brazed to the ceramic plate is less than 0.1 wt %, and Fe concentration of the circuit layer at a side of the surface opposite to the surface to be brazed is more than or equal to 0.1 wt %.

Abstract translation: 一种功率元件安装基板，包括钎焊到陶瓷板的表面的电路层和焊接到电路层的前表面的功率元件，其中电路层使用平均纯度大于或等于 等于98.0重量％且小于或等于99.9重量％时，要钎焊到陶瓷板的表面侧的电路层的Fe浓度小于0.1重量％，电路层的铁浓度在 与钎焊表面相对的表面的一侧大于或等于0.1重量％。

公开(公告)号：US08168288B2

公开(公告)日：2012-05-01

申请号：US12548661

申请日：2009-08-27

Applicant: Masato Nomiya ,  Satoshi Asakura ,  Tatsuya Ueda ,  Akira Baba

Inventor： Masato Nomiya ,  Satoshi Asakura ,  Tatsuya Ueda ,  Akira Baba

IPC: H05K1/11 ,  B32B17/06 ,  B22F3/10 ,  C04B35/64

CPC classification number: H05K3/38 ,  B32B18/00 ,  C04B2235/36 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/345 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/62 ,  C04B2237/68 ,  C04B2237/704 ,  H05K1/0306 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  Y10T428/12056 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: In a multilayer ceramic substrate manufactured by a non-shrinking process, a bonding strength of an external conductive film formed on a primary surface of the multilayer ceramic substrate is increased. After a laminate of a multilayer ceramic substrate is formed from first ceramic layers and second shrinkage suppressing ceramic layers, and an underlayer is formed along one primary surface of the multilayer ceramic substrate, an external conductive film is formed on the underlayer. A non-sintering ceramic material powder in a non-sintered state is included in both the external conductive film and the underlayer, and this non-sintering ceramic material powder is fixed due to diffusion of a glass component from the first ceramic layers.

Abstract translation: 在通过非收缩工艺制造的多层陶瓷基板中，形成在多层陶瓷基板的主表面上的外部导电膜的接合强度增加。 在由第一陶瓷层和第二收缩抑制陶瓷层形成多层陶瓷基板的层压体之后，沿着多层陶瓷基板的一个主面形成下层，在底层上形成外部导电膜。 外部导电膜和底层都包含非烧结状态的非烧结陶瓷材料粉末，由于来自第一陶瓷层的玻璃成分的扩散，这种非烧结陶瓷材料粉末被固定。

公开(公告)号：US08154123B2

公开(公告)日：2012-04-10

申请号：US12707872

申请日：2010-02-18

Applicant: Shigeru Kondou ,  Yoshihiro Tomura

Inventor： Shigeru Kondou ,  Yoshihiro Tomura

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2203/0292 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/207

Abstract: A solder bump and a conductive connection structure are provided which can conductively connect a semiconductor chip and a substrate with high connection reliability. Filler 5 is contained in a solder bump 6 and a solder joint 17 which connect a connection electrode 3 of a semiconductor chip 2 and a substrate 11, and the filler has a larger density on the side of the connection electrode 3 than on the side of the substrate 11 in the solder joint 17. Therefore, in the cooling solidification of solder, the shrinkage of the solder joint 17 near the connection electrode 3 of the semiconductor chip 2 is reduced by the filler 5 and the occurrence of a stress is reduced on the peripheral portion of the connection electrode 3, thereby preventing the occurrence of cracks near the joint.

Abstract translation: 提供了一种焊料凸块和导电连接结构，其可以以高连接可靠性导电地连接半导体芯片和基板。 填料5包含在焊料凸块6和连接半导体芯片2的连接电极3和基板11的焊接接头17上，并且填料在连接电极3的一侧具有比在侧面 因此，在焊料的冷却固化中，通过填料5减少了半导体芯片2的连接电极3附近的焊料接合部17的收缩，并且减少了应力的发生 连接电极3的周边部分，从而防止在接头附近发生裂纹。

公开(公告)号：US20100213609A1

公开(公告)日：2010-08-26

申请号：US12707872

申请日：2010-02-18

Applicant: Shigeru Kondou ,  Yoshihiro Tomura

Inventor： Shigeru Kondou ,  Yoshihiro Tomura

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2203/0292 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/207

Abstract: A solder bump and a conductive connection structure are provided which can conductively connect a semiconductor chip and a substrate with high connection reliability. Filler 5 is contained in a solder bump 6 and a solder joint 17 which connect a connection electrode 3 of a semiconductor chip 2 and a substrate 11, and the filler has a larger density on the side of the connection electrode 3 than on the side of the substrate 11 in the solder joint 17. Therefore, in the cooling solidification of solder, the shrinkage of the solder joint 17 near the connection electrode 3 of the semiconductor chip 2 is reduced by the filler 5 and the occurrence of a stress is reduced on the peripheral portion of the connection electrode 3, thereby preventing the occurrence of cracks near the joint.

Abstract translation: 提供了一种焊料凸块和导电连接结构，其可以以高连接可靠性导电地连接半导体芯片和基板。 填料5包含在焊料凸块6和连接半导体芯片2的连接电极3和基板11的焊接接头17上，并且填料在连接电极3的一侧具有比在侧面 因此，在焊料的冷却固化中，通过填料5减少了半导体芯片2的连接电极3附近的焊料接合部17的收缩，并且减少了应力的发生 连接电极3的周边部分，从而防止在接头附近发生裂纹。

公开(公告)号：US20090117357A1

公开(公告)日：2009-05-07

申请号：US12265561

申请日：2008-11-05

Applicant: Beom Joon CHO ,  Jong Myeon Lee ,  Myung Whun Chang

Inventor： Beom Joon CHO ,  Jong Myeon Lee ,  Myung Whun Chang

IPC: B32B18/00 ,  B32B5/16 ,  C04B35/00

CPC classification number: B32B18/00 ,  C04B35/638 ,  C04B2235/3217 ,  C04B2235/5292 ,  C04B2235/5436 ,  C04B2235/6562 ,  C04B2235/6567 ,  C04B2235/721 ,  C04B2235/9615 ,  C04B2237/562 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/0269 ,  H05K2203/308 ,  Y10T428/24942 ,  Y10T428/2495 ,  Y10T428/25 ,  Y10T428/252

Abstract: There is provided a hard-to-sinter constraining green sheet and a method of manufacturing a multilayer ceramic substrate using the same. The hard-to-sinter constraining green sheet disposed at least one of top and bottom surfaces of a non-sintered multi-layer ceramic substrate, the hard-to-sinter constraining green sheet including: a first constraining layer having a surface to be positioned on the multi-layer ceramic substrate, the first constraining layer including a first organic binder and a first inorganic binder having a spherical shape or a quasi-spherical shape; and a second constraining layer bonded to a top surface of the first constraining layer and including a second organic binder and a second inorganic powder having a flake shape, the second constraining layer having a powder packing density lower than a powder packing density of the first constraining layer.

Abstract translation: 提供了难以烧结的约束生片和使用其制造多层陶瓷基板的方法。 所述难烧结约束生片设置在非烧结多层陶瓷衬底的顶表面和底表面中的至少一个上，所述难烧结约束生片包括：具有待定位表面的第一约束层 在多层陶瓷基板上，第一约束层包括第一有机粘合剂和具有球形或准球形的第一无机粘合剂; 以及第二约束层，其结合到所述第一约束层的顶表面并且包括第二有机粘合剂和具有片状的第二无机粉末，所述第二约束层的粉末填充密度低于所述第一约束层的粉末堆积密度 层。

公开(公告)号：US07473853B2

公开(公告)日：2009-01-06

申请号：US11362516

申请日：2006-02-27

Applicant: Makoto Murai ,  Ryosuke Usui

Inventor： Makoto Murai ,  Ryosuke Usui

IPC: H05K1/16

CPC classification number: C23C28/00 ,  C23C28/322 ,  C23C28/345 ,  H01L23/3121 ,  H01L23/3733 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0315 ,  Y10T428/24331 ,  Y10T428/24917 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: The present invention provides a circuit device capable of controlling deformation of a circuit device while preventing an insulating layer from peeling from a substrate. The circuit device includes a substrate, an insulating layer formed on the substrate, a filler filled into the insulating layer, a conductive layer formed on the insulating layer, and a circuit element formed on the conductive layer, wherein an average particle diameter of the filler filled into the insulating layer is controlled so that a Young's modulus of a part of the insulating layer on a substrate side can be smaller than a Young's modulus of a part of the insulating layer on an opposite side relative to the substrate side.

Abstract translation: 本发明提供一种能够控制电路装置的变形同时防止绝缘层从基板剥离的电路装置。 该电路装置包括基板，形成在基板上的绝缘层，填充到绝缘层中的填充物，形成在绝缘层上的导电层和形成在导电层上的电路元件，其中填料的平均粒径 控制填充到绝缘层中，使得基板侧的绝缘层的一部分的杨氏模量可以小于相对于基板侧的相对侧的绝缘层的一部分的杨氏模量。

公开(公告)号：US07179684B2

公开(公告)日：2007-02-20

申请号：US11099907

申请日：2005-04-05

Applicant: Song-Hua Shi ,  Lejun Wang ,  Tian-An Chen

Inventor： Song-Hua Shi ,  Lejun Wang ,  Tian-An Chen

IPC: H01L21/00 ,  H01L21/58

CPC classification number: C08G73/02 ,  B32B27/08 ,  C08L79/02 ,  C09J161/34 ,  C09J179/04 ,  H01B3/303 ,  H01B3/38 ,  H01L21/563 ,  H01L23/293 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/323 ,  H05K2201/0269 ,  Y10T428/12528 ,  Y10T428/31511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: Microelectronic and optoelectronic packaging embodiments are described with underfill materials including polybenzoxazine, having the general formula:

公开(公告)号：US20030190477A1

公开(公告)日：2003-10-09

申请号：US10104830

申请日：2002-03-22

Inventor： Song-Hua Shi ,  Lejun Wang ,  Tian-An Chen

IPC: B32B027/38

CPC classification number: C08G73/02 ,  B32B27/08 ,  C08L79/02 ,  C09J161/34 ,  C09J179/04 ,  H01B3/303 ,  H01B3/38 ,  H01L21/563 ,  H01L23/293 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/323 ,  H05K2201/0269 ,  Y10T428/12528 ,  Y10T428/31511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: Microelectronic and optoelectronic packaging embodiments are described with underfill materials including polybenzoxazine, having the general formula: 1

Abstract translation: 使用具有以下通式的聚苯并恶嗪的底部填充材料描述微电子和光电子封装实施例：