公开(公告)号：US09338882B2

公开(公告)日：2016-05-10

申请号：US14278330

申请日：2014-05-15

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Raul Enriquez Shibayama ,  Gong Ouyang

IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08 ,  H01P11/00 ,  B33Y10/00 ,  B33Y80/00

CPC classification number: H05K1/0245 ,  B33Y10/00 ,  B33Y80/00 ,  H01P3/02 ,  H01P3/08 ,  H01P11/003 ,  H05K2201/09281 ,  Y10T29/49156

Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.

Abstract translation: 这里描述了宽边耦合差分设计。 该设计可以包括差分对。 差分对的每个迹线包括宽部分和窄部分。 差分对的第一迹线的宽部分将与差分对的第二迹线的窄部分对准。 此外，差分对的第二迹线的宽部分将与差分对的第一迹线的窄部分对齐，使得差分对的迹线的宽和窄部分交错。

公开(公告)号：US09282633B2

公开(公告)日：2016-03-08

申请号：US13519374

申请日：2012-06-11

Applicant: Hua Zheng ,  Cheng-hung Chen

Inventor： Hua Zheng ,  Cheng-hung Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0269 ,  H05K1/0289 ,  H05K2201/09281 ,  H05K2201/09936

Abstract: The present invention provides a routing structure and display panel. The routing structure includes a plurality of routing, disposed separately. Each routing corresponds to a symbol, and the symbol is disposed on the routing to act as a part of the routing to conduct electricity. In this manner, the routing structure and display panel of the present invention allow expansion of routing width, effectively reduce RC constant and energy-consumption, and improve yield rate.

Abstract translation: 本发明提供一种路由结构和显示面板。 路由结构包括多个路由，分开设置。 每个路由对应于符号，并且该符号被布置在路由上以充当路由的一部分以进行电力。 以这种方式，本发明的路由结构和显示面板允许扩展路由宽度，有效降低RC常数和能量消耗，并提高成品率。

公开(公告)号：US20150129284A1

公开(公告)日：2015-05-14

申请号：US14076667

申请日：2013-11-11

Applicant: Seagate Technology LLC

Inventor： Prapan Aparimarn ,  Chaovalit Chiyatan ,  Piriyakorn Jirawattanakasem ,  Joompondej Bamrungwongtaree

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/111 ,  G11B5/486 ,  H05K1/0296 ,  H05K1/056 ,  H05K1/11 ,  H05K3/3436 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09727 ,  Y02P70/611

Abstract: A printed circuit substrate may be configured with at least one internal lead designed and shaped to reduce solder bridging. The printed circuit substrate can have a plurality of internal leads that each has a continuously curvilinear boundary that defines an isolation channel. The isolation channel may be configured with a uniform distance that separates a first internal lead from an adjacent second internal lead.

Abstract translation: 印刷电路基板可以配置有至少一个设计和成形以减少焊料桥接的内部引线。 印刷电路基板可以具有多个内部引线，每个内部引线具有限定隔离通道的连续曲线边界。 隔离通道可以配置有将第一内部引线与相邻的第二内部引线分开的均匀距离。

公开(公告)号：US20150060395A1

公开(公告)日：2015-03-05

申请号：US14012240

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一印模和多级第二印模。 在基板上设置有可固化的底层和多层。 底层微通道印在底层中。 多层微通道和顶层微通道印在多层中。 微线形成在每个微通道中。 底层微线从中心区域延伸到边缘区域。 多层微线接触边缘区域的底层微线。 顶层微线在中心区域之上，与多层微线和底层微通道分离。 底层微线电连接到多层微线，并与顶层微线电隔离。

公开(公告)号：US20150060394A1

公开(公告)日：2015-03-05

申请号：US14012216

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一，第二和第三不同的邮票。 在基板上形成可固化的底部，连接层和顶层。 底层微通道印在中心区域和边缘区域的底层中，连接层微通道被压印在底层微通道上的边缘区域中的连接层中，边缘 微通道印在连接层微通道上的边缘区域的顶层中，顶层微通道印在中心区域的顶层中。 微线形成在每个微通道中。 中心区域的底层微线电连接到边缘区域中的边缘微线，并与顶层微线电隔离。

公开(公告)号：US20130201637A1

公开(公告)日：2013-08-08

申请号：US13574789

申请日：2011-01-31

Applicant: Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

Inventor： Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

IPC: H05K1/02 ,  H05K13/04 ,  H05B33/08

CPC classification number: H05K1/0277 ,  G09F9/00 ,  G09F19/22 ,  H01L27/3293 ,  H01L31/0392 ,  H01L31/042 ,  H01L51/5203 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01R4/04 ,  H01R4/70 ,  H01R12/7076 ,  H05B33/0896 ,  H05B33/10 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/147 ,  H05K1/189 ,  H05K3/321 ,  H05K3/325 ,  H05K3/365 ,  H05K13/04 ,  H05K2201/029 ,  H05K2201/0311 ,  H05K2201/046 ,  H05K2201/083 ,  H05K2201/09081 ,  H05K2201/09281 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10484 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An assembly of a plurality of tiles (1) with a carrier (40), wherein the tiles (1) comprise a foil (20) with an electro-physical transducer (10) and electrical connectors (24, 28) to said transducer. The tiles are mechanically and electrically coupled to the carrier, and the tiles overlay according to a fish scale pattern.

Abstract translation: 具有载体（40）的多个瓦片（1）的组件，其中瓦片（1）包括具有电 - 物理换能器（10）的箔（20）和到所述换能器的电连接器（24,28）。 瓦片机械地和电耦合到载体上，并且瓦片根据鱼鳞图案覆盖。

公开(公告)号：US08476533B2

公开(公告)日：2013-07-02

申请号：US13238761

申请日：2011-09-21

Applicant: Fa-Ping Fan

Inventor： Fa-Ping Fan

IPC: H05K1/03

CPC classification number: H05K1/111 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09281 ,  Y02P70/611

Abstract: An exemplary printed circuit board includes a substrate, a differential transmission line, and at least two weld pad pairs. The differential transmission line and the at least two weld pad pairs are disposed on the substrate. The differential transmission line includes two parallel signal conductors disposed on the substrate. Each of the two signal conductors is electrically connected to an edge of one of the weld pads of a respective pair of the at least two weld pad pairs. Thereby, the two signal conductors of the differential transmission line can extend in the same distance anywhere, particularly in the position where the two signal conductors pass the two weld pad pairs. As a result, the coupling performance and the capability of the differential transmission line to resist electromagnetic interference are both enhanced.

Abstract translation: 示例性印刷电路板包括基板，差分传输线和至少两个焊盘对。 差分传输线和至少两个焊盘对设置在基板上。 差分传输线包括设置在基板上的两个并行信号导体。 两个信号导体中的每一个电连接到相应的一对至少两个焊盘对的焊接焊盘之一的边缘。 因此，差分传输线的两个信号导体可以在任何地方延伸相同的距离，特别是在两个信号导体通过两个焊盘对的位置。 结果，提高了耦合性能和差动传输线抵抗电磁干扰的能力。

公开(公告)号：US08222749B2

公开(公告)日：2012-07-17

申请号：US12254382

申请日：2008-10-20

Applicant: Seiji Sato ,  Takashi Ozawa

Inventor： Seiji Sato ,  Takashi Ozawa

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/3484 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/014

Abstract: A wiring substrate of the present invention includes such a structure that a plurality of connection pads and leading wiring portions connected to the plurality of connection pads respectively are arranged to an insulating layer of a surface layer side, and the leading wiring portions are arranged to be bended from the connection pads, and a solder layer to protrude upward is provided on the connection pads respectively. A solder on the leading wiring portions moves to the bend portion side, and thus the solder layer to protrude upward is formed on the connection pads.

Abstract translation: 本发明的布线基板包括将多个连接焊盘和连接到多个连接焊盘的引线布线部分分别布置到表面层侧的绝缘层的结构，并且引导布线部分布置成 从连接焊盘弯曲，分别在连接焊盘上设置向上突出的焊料层。 前导布线部分上的焊料移动到弯曲部分侧，因此在连接焊盘上形成向上突出的焊料层。

公开(公告)号：US07806731B2

公开(公告)日：2010-10-05

申请号：US11321931

申请日：2005-12-29

Applicant: Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01R24/00

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/117 ,  H05K3/242 ,  H05K3/3452 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract translation: 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20100096170A1

公开(公告)日：2010-04-22

申请号：US12645303

申请日：2009-12-22

Applicant: YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

Inventor： YU-HSU LIN ,  JENG-DA WU ,  CHIH-HANG CHAO

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09281 ,  H05K2201/09681 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit board includes a signal plane and a ground plane. The signal plane is configured to have a plurality of signal traces arranged thereon. Each of the signal traces includes a plurality of straight line segments. Each line segment extends along a path different from the others. The ground plane includes a plurality of tiles connected in an array. Each tile is formed by ground traces. The straight line segments of each signal trace mapped on the ground plane are arranged at an angle relative to any one ground trace of the tiles. The angle is defined within a range determined by one of ground traces of a tile and an adjacent diagonal line of the tile. A method for laying out such a circuit board is also provided.

Abstract translation: 电路板包括信号平面和接地平面。 信号平面被配置为具有布置在其上的多个信号迹线。 每个信号迹线包括多个直线段。 每个线段沿着与其他线不同的路径延伸。 接地平面包括以阵列连接的多个瓦。 每个瓷砖由地面痕迹形成。 映射在接地平面上的每个信号迹线的直线段相对于瓦片的任何一个接地迹线以一定角度布置。 该角度限定在由瓦片的接地轨迹和瓦片的相邻对角线之一确定的范围内。 还提供了布线这种电路板的方法。