公开(公告)号：KR101490758B1

公开(公告)日：2015-02-06

申请号：KR1020140085331

申请日：2014-07-08

Applicant: 피에스아이 주식회사

Inventor： 도영락

IPC: H01L33/36

CPC classification number: H01L25/0753 ,  H01L33/38 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0066 ,  H05K1/0295 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09427 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2201/10583 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2203/048 ,  Y02P70/611 ,  H01L2924/00

Abstract: 본 발명은 초소형 LED 전극어셈블리 및 이의 제조방법에 관한 것으로, 보다 상세하게는 첫째로, 독립하여 제조된 초소형 LED 소자를 불량 없이 서로 다른 두 전극에 정렬하여 연결시킴으로써 나노단위의 초소형 LED 소자를 서로 다른 전극에 직립으로 결합시키는 난점을 극복할 수 있다. 또한 LED 소자와 연결되는 전극을 동일평면상에 위치시킴으로써 결과적으로 LED 소자의 광추출 효율을 향상시킬 수 있다. 나아가 서로 다른 전극과 연결되는 초소형 LED 소자의 개수를 조절할 수 있다. 둘째로, 초소형 LED 소자가 직립하여 상, 하부 전극과 3차원 결합하지 않고 누운 상태로 동일평면상에 존재하는 서로 다른 전극에 결합함으로써 매우 우수한 광추출 효율을 가지며, LED 소자의 표면에 별도의 층을 형성하여 LED 소자와 전극 간에 단락을 방지함으로써 LED 전극어셈블리의 불량률을 최소화할 수 있으며 만일하나 발생할 수 있는 LED 소자의 불량을 대비하여 복수개의 LED 소자를 전극과 연결시킴으로써 초소형 LED 전극어셈블리 본래의 기능을 유지할 수 있다.

公开(公告)号：KR1020090130783A

公开(公告)日：2009-12-24

申请号：KR1020080056566

申请日：2008-06-16

Applicant: 삼성전기주식회사

Inventor： 윤관수 ,  프라사드제이비비 ,  정재우 ,  서상훈 ,  조상도

IPC: G06F3/12 ,  B41J2/00

CPC classification number: H05K3/125 ,  H05K1/11 ,  H05K3/0005 ,  H05K3/0008 ,  H05K2201/0939

Abstract: PURPOSE: An image data processing method and a recording medium are provided to print a pad with high reliability and high surface flatness suitable for a user's required resolution and ink density. CONSTITUTION: Vector data for a pad is arranged on an x/y coordinates system(S120). On the coordinates system, a first reference point is set(S130). In one direction of 45 degrees and 135 degrees from the first reference point, a first decision point is selected(S140). The first decision point is separated as x-axis and y-axis unit distances. A distance to first decision point from the first reference point is compared with a reference pitch(S150). If the distance is larger than or equal to the reference pitch, coordinates of the first decision point are stored as printing data.

Abstract translation: 目的：提供一种图像数据处理方法和记录介质，以便打印具有高可靠性和高表面平整度的垫，其适合于用户所需的分辨率和墨密度。 构成：用于焊盘的矢量数据安排在x / y坐标系上（S120）。 在坐标系上，设定第一参考点（S130）。 在与第一参考点成45度和135度的一个方向上，选择第一判定点（S140）。 第一个决策点被分离为x轴和y轴单位距离。 将与第一参考点的第一判定点的距离与参考间距进行比较（S150）。 如果距离大于或等于基准间距，则将第一判定点的坐标存储为打印数据。

公开(公告)号：KR1020060062404A

公开(公告)日：2006-06-12

申请号：KR1020040101231

申请日：2004-12-03

Applicant: 삼성전자주식회사

Inventor： 김광렬

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/116 ,  H05K1/182 ,  H05K3/3405 ,  H05K3/3457 ,  H05K2201/0939

Abstract: 본 발명은 납성분이 제외된 무연솔더에 의해 전기부품이 고정 및 접속되는 인쇄회로기판에 관한 것이다.
본 발명에 따른 인쇄회로기판은 복수의 접속핀을 구비한 전기부품이 설치되며, 복수의 접속핀이 각각 삽입되어 무연솔더의 솔더링을 통해 고정되는 복수의 설치공이 마련되어 있는 것으로, 설치공은 일방향으로 길게 연장형성되어 소정길이의 단축과 단축에 비하여 상대적으로 긴 길이를 갖는 장축을 갖도록 형성되어 있으므로, 이웃한 설치공과의 간격은 일정하게 유지하면서 설치공의 장축측 내면과 접속핀의 외면 사이에 양단부에 무연솔더가 스며들기에 충분한 공간을 확보할 수 있게 되는 작용효과가 있다.

公开(公告)号：US20240314929A1

公开(公告)日：2024-09-19

申请号：US18588633

申请日：2024-02-27

Applicant: Kioxia Corporation

Inventor： Kiyokazu ISHIZAKI

IPC: H05K1/11 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H05K1/18

CPC classification number: H05K1/117 ,  H01L23/3128 ,  H01L23/49816 ,  H01L25/0652 ,  H05K1/111 ,  H05K1/181 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586 ,  H05K2201/0939 ,  H05K2201/09409 ,  H05K2201/10734 ,  H05K2201/10984

Abstract: A semiconductor storage device includes a wiring pattern on an insulating base material; an insulating film covering partially the wiring pattern; and an electronic component. The wiring pattern includes a first pad having an edge in an arc shape, and a first wire. The insulating film has a first opening larger than the first pad. The first wire has a first portion, a second portion, and a third portion. The first portion is connected to the first pad inside the first opening extends in a first direction. The second portion is connected to the first pad inside the first opening and extends in a second direction. The third portion is connected to the first portion and the second portion. The first wire is connected with the first pad in an angular range of not more than 90 degrees in a circumferential direction of the first pad.

公开(公告)号：US12063737B2

公开(公告)日：2024-08-13

申请号：US17921778

申请日：2021-04-26

Applicant: LG INNOTEK CO., LTD.

Inventor： Hae Sik Kim ,  Jee Heum Paik

IPC: H05K1/02 ,  H04N23/68 ,  H05K1/11

CPC classification number: H05K1/0296 ,  H04N23/687 ,  H05K1/116 ,  H05K2201/0939 ,  H05K2201/09618 ,  H05K2201/10151 ,  H05K2201/10287

Abstract: A circuit board according to an embodiment includes an insulating layer; and a lead pattern portion disposed on the insulating layer, wherein the lead pattern portion includes: a first portion disposed on the insulating layer; and a second portion extending from one end of the first portion; wherein the first portion is disposed overlapping the insulating layer in a vertical direction, wherein the second portion is disposed in an outer region of the insulating layer and does not overlap the insulating layer; and wherein the lead pattern portion has a centerline average roughness in a range of 0.05 μm to 0.5 μm or a 10-point average roughness in a range of 1.0 μm to 5.0 μm.

公开(公告)号：US20230422398A1

公开(公告)日：2023-12-28

申请号：US17818722

申请日：2022-08-10

Applicant: GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Chieh LIAO ,  Yu-Min SUN ,  Chih-Feng CHENG

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/31 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K1/111 ,  H05K1/181 ,  H01L23/3128 ,  H05K3/0005 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/0939 ,  H05K2201/094 ,  H05K2201/09418 ,  H01L23/13

Abstract: An electric device includes a semiconductor assembly, a circuit board, first conductive pads and second conductive pads. The circuit board has a chip-mounted area with a rectangular shape. The first conductive pads are arranged in a center zone or all corner zones of the chip-mounted area, and the second conductive pads are arranged within the rest in the chip-mounted area. The first conductive pads are respectively soldered to one part of solder joints of the semiconductor assembly through first solder-ball portions, and the second conductive pads are respectively soldered to another part of the solder joints of the semiconductor assembly through second solder-ball portions. Each of the second conductive pads is sized smaller than one of the first conductive pads, and a maximum width of each of the second solder-ball portions is greater than a maximum width of each of the first solder-ball portions.

公开(公告)号：US20230209713A1

公开(公告)日：2023-06-29

申请号：US17672330

申请日：2022-02-15

Applicant: KINPO ELECTRONICS, INC.

Inventor： Chuan-Wang CHANG ,  Yu-Ta LIN ,  Chen-Jung CHEN

IPC: H05K1/11 ,  H01L23/49 ,  H01L23/00

CPC classification number: H05K1/119 ,  H01L23/49 ,  H01L24/49 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2224/49173 ,  H05K2201/09027 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/0939 ,  H05K2201/094

Abstract: A pad arranging method and a pad arrangement structure for a wire bonding of a chip is provided. The method includes following steps. A soldered component and a circuit board are provided. A plurality of pads is arranged on the circuit board. a number of the pads is corresponding to a number of a plurality pins of the soldered component. The pads are disposed in a plurality of rows toward or away from the soldered component according to a predetermined arranging position, and the number of the pads on one of the rows at outer side is equal to that on one of the rows at inner side, or greater than that on one of the rows at inner side by one or more than one

公开(公告)号：US20180338377A1

公开(公告)日：2018-11-22

申请号：US15543995

申请日：2017-05-09

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Qingcheng ZUO

IPC: H05K1/14 ,  H05K1/11

CPC classification number: H05K1/147 ,  G02F1/133308 ,  G02F1/13454 ,  G02F2001/13456 ,  H05K1/118 ,  H05K2201/0939 ,  H05K2201/10128

Abstract: The embodiment of the present invention discloses a narrow frame display panel, comprising: an integrated circuit input pad, being located on a lower side of the display panel and comprising a plurality of input terminals; a flexible printed circuit bonding pad, being located on a lower edge of the display panel and below the integrated circuit input pad, and the flexible printed circuit bonding pad comprising a plurality of bonding terminals, and bonding terminals of at least one end of the flexible printed circuit bonding pad are first bonding terminals, wherein each of the first bonding terminals comprising at least one three-side bracketing structure extending outward in a horizontal direction; wires, electrically connecting the integrated circuit input pad with the flexible printed circuit bonding pad. The embodiment of the present invention further discloses a display. By utilizing the present invention, being advantageous for narrow frame design is achieved.

公开(公告)号：US10038264B2

公开(公告)日：2018-07-31

申请号：US15351237

申请日：2016-11-14

Applicant: Microsoft Technology Licensing, LLC

Inventor： David Lukofsky ,  Joseph Christopher Bolling ,  Jeffrey M. Quackenbush ,  Tapani von Rauner

IPC: H01R12/00 ,  H01R12/91 ,  H01R12/78 ,  H01R12/72 ,  H04N13/04

CPC classification number: H01R12/91 ,  H01R12/721 ,  H01R12/78 ,  H04N13/344 ,  H04N2213/001 ,  H04N2213/008 ,  H05K1/0221 ,  H05K1/0295 ,  H05K1/11 ,  H05K3/361 ,  H05K2201/09272 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: A universal coupling is disclosed for electrically and mechanically connecting flexible printed circuit (FPC) components within asymmetric FPC modules. The universal coupling allows a first FPC component to be connected to a second FPC component in two or more different orientations. This allows identical FPC components to be used in two or more asymmetric FPC modules. This in turn allows a reduction in the number of parts and tooling required to fabricate the two or more asymmetric FPC modules, and a simplification of the fabrication process.

公开(公告)号：US09480141B1

公开(公告)日：2016-10-25

申请号：US14032908

申请日：2013-09-20

Applicant: Junis Hamadeh

Inventor： Junis Hamadeh

IPC: H05K1/02 ,  H01R12/00

CPC classification number: H01R12/00 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09463 ,  H05K2201/0959 ,  H05K2201/10106 ,  H05K2201/10401 ,  H05K2201/10416

Abstract: A heat sinking rapid assembly semiconductor package comprising an electrically segmented conductive assembly post. The post is fabricated comprising at least two independent electrically conductive segments separated by an electrically isolating element. An electrical component, such as a semiconductor device, is assembled to an upper portion of the conductive post, wherein each contact of the component is in electrical communication with a respective conductive segment. The post can be mechanically pressed, threaded, or mechanically coupled using any other reasonable mechanical interface into a segmented via or plated-through hole of a printed circuit board (PCB). The electrical segments would be in electrical communication with conductive portions of the segmented via to form a complete electrical circuit between the PCB and the electrical component. A thermally conductive element can be integrated into the post to conduct heat away from the semiconductor device to improve performance and reduce failures related to thermal stress.

Abstract translation: 一种散热快速组装半导体封装，包括电分段的导电组件柱。 该柱被制造成包括由电隔离元件隔开的至少两个独立的导电段。 诸如半导体器件的电气部件被组装到导电柱的上部，其中部件的每个触点与相应的导电部分电连通。 可以使用任何其他合理的机械接口将柱机械地压制，螺纹化或机械耦合到印刷电路板（PCB）的分段通孔或电镀通孔中。 电段将与分段通孔的导电部分电连通，以在PCB和电气部件之间形成完整的电路。 导热元件可以集成到柱中以将热量从半导体器件导出，以提高性能并减少与热应力相关的故障。