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公开(公告)号：KR1020110136643A
公开(公告)日：2011-12-21
申请号：KR1020100056780
申请日：2010-06-15
Applicant: 서울대학교산학협력단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/0688 , B82Y10/00 , H01L21/823425 , Y10S977/762
Abstract: PURPOSE: A nanowire device capable of a body contact and a 3D stack NAND flash memory array using the same are provided to erase a block with only one body contact through a body contact line. CONSTITUTION: An active body(30) is formed in the form of a nanowire. A gate(60) is formed between a gate insulating layers(42). A first source/drain(32) and a second source/drain(80) are formed in the both sides of the gate. A body area(30b), which is integrally formed with the active body, exist in the inner sides of the first source/drain and the second source/drain . The diameter of the body area is the same as or smaller than that of the active body.
Abstract translation: 目的：提供能够接触身体的纳米线器件和使用其的3D堆叠NAND快闪存储器阵列，以通过身体接触线仅擦去一个身体接触的块。 构成：以纳米线的形式形成活性体（30）。 栅极（60）形成在栅绝缘层（42）之间。 第一源极/漏极（32）和第二源极/漏极（80）形成在栅极的两侧。 与主动体一体形成的主体区域30b存在于第一源极/漏极和第二源极/漏极的内侧。 身体区域的直径与活体的直径相同或更小。
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公开(公告)号：KR1020110136642A
公开(公告)日：2011-12-21
申请号：KR1020100056779
申请日：2010-06-15
Applicant: 서울대학교산학협력단
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/0688 , H01L21/76256 , H01L27/10882 , H01L27/11551 , H01L27/11578 , H01L27/2463 , H01L27/2481
Abstract: PURPOSE: A 3D stack NAND flash memory array with a connection gate and a manufacturing method thereof are provided to simultaneously form a plurality of layer selection line which is self-aligned by performing an etch back etching process anisotropically. CONSTITUTION: A bit line includes a plurality of semiconductor layers(31,32,33). The plurality of the semiconductor layers is perpendicularly laminated on a substrate(10) while having a space with an insulating layer(20). A plurality of word lines(51,52) is formed while being isolated with a certain distance to a x-axis. The insulating layer includes a charge storage layer which is vertical with each bit line. A plurality of active lines is respectively extended to one side of the plurality of the word lines.
Abstract translation: 目的：提供具有连接栅极及其制造方法的3D堆叠NAND闪速存储器阵列，以通过各向异性地执行回蚀刻工艺来同时形成多个层选择线，该层选择线是自对准的。 构成：位线包括多个半导体层（31,32,33）。 多个半导体层在具有绝缘层（20）的空间的同时垂直地层叠在基板（10）上。 多个字线（51,52）形成为与x轴一定距离隔离。 绝缘层包括与每个位线垂直的电荷存储层。 多条有效线分别延伸到多条字线的一侧。
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公开(公告)号：KR1020110136641A
公开(公告)日：2011-12-21
申请号：KR1020100056778
申请日：2010-06-15
Applicant: 서울대학교산학협력단
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/78696 , H01L21/02225 , H01L29/4232 , H01L29/66348
Abstract: PURPOSE: A single electron transistor and a process method thereof are provided to form a tunneling barrier on a channel without bias approval by forming a material, which has a work function difference with the recessed channel, into a side gate. CONSTITUTION: Silicon layers(14,16) have a recessed channel area on the filled oxide layer of a SOI substrate. A first gate insulating layer(80) is formed on the channel area. A first and a second side gate(92) are formed between the first gate insulating layers. The first and the second side gate are formed into the material which has a work function difference with the recessed channel. A control gate(66a) is formed on the filled oxide layer between second gate insulating layers(82a).
Abstract translation: 目的：提供单电子晶体管及其处理方法，以在通道上形成隧道势垒，而不需要通过形成与凹陷通道的功函数差异的材料进入侧浇口来进行偏压认证。 构成：硅层（14,16）在SOI衬底的填充氧化物层上具有凹陷的沟道区域。 第一栅绝缘层（80）形成在沟道区上。 第一和第二侧栅极（92）形成在第一栅极绝缘层之间。 第一和第二侧门形成与凹陷通道具有功函数差异的材料。 在第二栅极绝缘层（82a）之间的填充氧化物层上形成控制栅极（66a）。
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公开(公告)号：KR1020110136532A
公开(公告)日：2011-12-21
申请号：KR1020100056615
申请日：2010-06-15
Applicant: 서울대학교산학협력단
IPC: H01L27/092
Abstract: PURPOSE: A 1T DRAM(Dynamic Random Access Memory) device which includes two gates in a depressed body, an operation method thereof, and a manufacturing method for the same are provided to independently apply negative voltage to the gate which is not overlapped with a drain, thereby significantly increasing data retention time. CONSTITUTION: A semiconductor body(32) is electrically isolated and depressed. A depressed part of the semiconductor body is arranged as a trench shape. A gate insulating film(52) is arranged in the depressed part of the semiconductor body. A first gate(62) and second gate(64) are filled in the depressed part of the semiconductor body. A source(72) and drain(74) are arranged with an N-type impurity doping layer.
Abstract translation: 目的：提供一种包括凹陷体中的两个栅极的1T DRAM（动态随机存取存储器）装置及其操作方法及其制造方法，以独立地向不与漏极重叠的栅极施加负电压 ，从而显着增加数据保留时间。 构成：半导体本体（32）被电隔离和压制。 将半导体本体的凹部配置为沟槽状。 栅极绝缘膜（52）布置在半导体本体的凹陷部分中。 第一栅极（62）和第二栅极（64）填充在半导体主体的凹陷部分中。 源极（72）和漏极（74）配置有N型杂质掺杂层。
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公开(公告)号：KR1020110133946A
公开(公告)日：2011-12-14
申请号：KR1020100053645
申请日：2010-06-08
Applicant: 서울대학교산학협력단
IPC: H01L29/775
CPC classification number: H01L29/7613 , H01L29/4983 , H01L29/66439
Abstract: PURPOSE: A single electron transistor using a work function difference and a manufacturing method thereof are provided to form a material whose work function is different from the work function of a channel area, thereby simply forming a tunneling barrier in a channel length direction. CONSTITUTION: A source area(22) and a drain area(24) are separated on a semiconductor substrate(20). A control gate(40) is formed between first gate insulating films on a channel area. Two sidewall spacer gates(52,54) are electrically separated from the control gate. A second gate insulating film is formed between the sidewall spacer gates. The sidewall spacer gates are formed on the channel area. Each sidewall gate is made of a material whose work function is different from the work function of the channel area.
Abstract translation: 目的：提供使用功函数差的单电子晶体管及其制造方法，以形成其功函数不同于沟道区的功函数的材料，从而简单地在沟道长度方向形成隧道势垒。 构成：在半导体衬底（20）上分离源区（22）和漏区（24）。 在通道区域上的第一栅极绝缘膜之间形成控制栅极（40）。 两个侧壁间隔栅极（52,54）与控制栅极电分离。 第二栅绝缘膜形成在侧壁间隔栅之间。 侧壁间隔栅极形成在沟道区域上。 每个侧壁门由其功能不同于通道区域的功能的材料制成。
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Patent Agency Ranking
公开(公告)号：KR101082423B1
公开(公告)日：2011-11-10
申请号：KR1020080138639
申请日：2008-12-31
Applicant: 서울대학교산학협력단
IPC: H01L29/78 , H01L29/775 , H01L21/336
Abstract: 본발명은단전자트랜지스터및 그제조방법에관한것으로, 특히, 금속(또는실리사이드)/산화막/실리콘의접촉에의한모스장벽을터널링장벽으로이용한것이어서, 금속과실리콘접촉시발생될수 있는계면트랩이나페르미레벨피닝(Fermi level pinning) 현상등을근본적으로막을수 있고, 모스장벽으로양자점의경계가명확하며, 금속의종류에따라장벽의높이를조절할수 있는장점이있고, 산화막으로전면이싸여진실리콘에양자점이형성되므로, 양자점의크기를최대한줄이면서도, 소스/드레인의저항이늘어나지않게하여, 상온동작이가능하게한 효과가있고, 본발명에의한제조방법은통상의 MOSFET 공정과유사하여, MOSFET과한 웨이퍼상에서동시제조가가능함에따라하이브리드회로구현이가능하고, 저온공정이므로게이트절연막으로고유전율을갖는물질도사용할수 있는효과가있다.
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公开(公告)号：KR101058880B1
公开(公告)日：2011-08-25
申请号：KR1020100042869
申请日：2010-05-07
Applicant: 서울대학교산학협력단
CPC classification number: H01L25/167 , H01L24/95 , H01L27/1214 , H01L27/1255 , H01L33/20 , H01L33/40 , H01L2224/95085 , H01L2924/01322 , H01L2924/12036 , H01L2924/12041 , H01L2924/12044 , H01L2924/00
Abstract: PURPOSE: An LED display device with an active element and a manufacturing method thereof are provided to efficiently manufacture AM-LED display device in a high temperature for a short time by forming a LED block receiving part and a transistor receiving part and coupling the transistor block of a single crystal silicon with an LED block by a FSA(Fluidic Self Assembly) method. CONSTITUTION: A buffer layer is formed on a substrate(3). A source and a drain are respectively formed in the both sides of active layers on a transistor for switching(7) and a transistor for driving(8) by being separated on a buffer layer in a pigment unit. A first insulating layer is formed on the substrate while covering the active layer of the transistor for driving. A scan line is formed crossing the source and the drain of the transistor for switching on a first insulating layer. The bottom electrode of a storage capacitor is electrically connected with the drain of the transistor for switching. A second insulating layer is formed on the first insulating layer while covering the scan line, the bottom electrode of the storage capacitor and a cathode line. A source supply line is electrically connected with the source of the transistor for driving on the second insulating layer. An anode interconnection layer is formed between a data line and the source supply line. An LED block receiving part is formed into a pigment unit on the second insulating layer while at least covering a part with a third insulating layer.
Abstract translation: 目的：提供一种具有有源元件的LED显示装置及其制造方法，用于通过形成LED块接收部和晶体管接收部来高效地制造高温下的AM-LED显示装置，并将晶体管块 的具有LED块的单晶硅通过FSA（流体自组装）方法。 构成：在基板（3）上形成缓冲层。 源极和漏极分别在用于开关（7）的晶体管和用于驱动（8）的晶体管的有源层的两侧分别形成在颜料单元中的缓冲层上。 在覆盖用于驱动的晶体管的有源层的同时，在衬底上形成第一绝缘层。 形成与晶体管的源极和漏极交叉的第一绝缘层的扫描线。 存储电容器的底部电极与用于切换的晶体管的漏极电连接。 在第一绝缘层上形成第二绝缘层，同时覆盖扫描线，存储电容器的底部电极和阴极线。 源极电源线与晶体管的源极电连接，用于在第二绝缘层上驱动。 在数据线和源电源线之间形成阳极互连层。 LED块接收部分形成为第二绝缘层上的颜料单元，同时至少用第三绝缘层覆盖一部分。
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公开(公告)号：KR1020110081623A
公开(公告)日：2011-07-14
申请号：KR1020100001878
申请日：2010-01-08
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
CPC classification number: G11C13/0002 , G11C13/0023 , G11C2213/71 , H01L27/101 , H01L27/102 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
Abstract: PURPOSE: A semiconductor devices and a method of driving the same are provided to implement high integration by preventing the interference between nonvolatile memory cells. CONSTITUTION: In a semiconductor devices and a method of driving the same, a unit cell structure(1) comprises electrode layers(M1,M2), a bipolar resistance memory material film(RM1), and a unipolar resistance memory material film(RM2) The bipolar resistance memory material film and the unipolar resistance memory material film are formed between electrode layers which are opposite to each other. The bipolar resistance memory material film and the unipolar resistance memory material film are electrically serially connected. The electrode layers include resistance memory material films which are connected to conductive lines respectively.
Abstract translation: 目的：提供半导体器件及其驱动方法，以通过防止非易失性存储单元之间的干扰来实现高集成度。 构成：在半导体器件及其驱动方法中，单元电池结构（1）包括电极层（M1，M2），双极性电阻记忆材料膜（RM1）和单极电阻存储材料膜（RM2） 双极性电阻记忆材料膜和单极电阻记忆材料膜形成在彼此相对的电极层之间。 双极性电阻记忆材料膜和单极性电阻记忆材料膜电连接。 电极层包括分别连接到导线的电阻记忆材料膜。
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公开(公告)号：KR101034975B1
公开(公告)日：2011-05-19
申请号：KR1020090062719
申请日：2009-07-09
Applicant: 서울대학교산학협력단
IPC: H01L27/115 , H01L21/8247
Abstract: 본 발명은 종래 RRAM 셀 구조에 전도 경로 개폐용으로 하나 이상의 PRAM 물질층을 삽입층으로 적절히 형성함으로써, PRAM 물질층의 갯수에 따라 2bit, 4bit 등으로 MLC 동작이 가능하게 하여 결과적으로 고집적성 RRAM 어레이 구현이 가능하게 한 PRAM 물질층을 삽입층으로 갖는 RRAM 셀 및 이를 이용한 RRAM 어레이에 관한 것이다.
PRAM, RRAM, 다중저항상태, MLC, 전이금속산화물, 켈코게나이드, GST-
公开(公告)号：KR101030983B1
公开(公告)日：2011-04-28
申请号：KR1020090062763
申请日：2009-07-09
Applicant: 서울대학교산학협력단
IPC: H01L29/812 , H01L21/338
Abstract: 본 발명은 비대칭 TFET의 구조 및 그 제조방법에 관한 것으로, 보다 상세하게는 자기 정렬된(self-aligned) 공정 및 측벽 공정을 통하여 나노 스케일의 짧은 채널을 갖고 소스를 금속 실리사이드로 형성함으로써, 소스와 채널 사이에 형성되는 쇼트키 장벽(Schottky barrier)을 이용한 TFET 및 그 제조방법에 관한 것이다.
비대칭, 쇼트키 장벽, TFET
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