公开(公告)号：JP2000216851A

公开(公告)日：2000-08-04

申请号：JP2000056058

申请日：2000-02-28

Applicant: SONY CORP

Inventor： YANAGIHARA HISAFUMI ,  KOMURO TERUYOSHI ,  SHIMA HISATO

IPC: H04N5/92 ,  H04L29/10 ,  H04N7/08 ,  H04N7/081 ,  H04N7/24 ,  H04N19/00 ,  H04N19/423 ,  H04N19/44 ,  H04N19/46 ,  H04N19/625 ,  H04N19/65 ,  H04N19/70 ,  H04N19/85 ,  H04N19/89 ,  H04N19/91

Abstract: PROBLEM TO BE SOLVED: To promptly perform decoding operation even when a program is switched in a transport stream to be transmitted when the transport stream is transmitted to other equipment via a digital interface. SOLUTION: Switching of the program in the transport stream of a reproduction signal is detected and informed to the digital interface 16 by a signal processing microcomputer 8. A discontinuous flag to indicate that the transport stream is discontinuous because switching of the program of the transport stream is caused on a header of an isochronous packet in which video data to be transmitted from a demultiplexer 12 are stored by the digital interface 16.

公开(公告)号：JPH1153264A

公开(公告)日：1999-02-26

申请号：JP21089997

申请日：1997-08-05

Applicant: SONY CORP

Inventor： ISHIGURO RYUJI ,  OSAWA YOSHITOMO ,  OSAKABE YOSHIO ,  SATO MAKOTO ,  SHIMA HISATO ,  NAKANO KATSUHIKO ,  ASANO TOMOYUKI

IPC: G06F12/14 ,  G06F1/00 ,  G06F21/00 ,  G06F21/24 ,  G11B19/04 ,  G11B19/12 ,  G11B20/00 ,  G11B20/10 ,  H04L9/08 ,  H04L12/40 ,  H04L12/64

Abstract: PROBLEM TO BE SOLVED: To prevent information from being copied illicitly. SOLUTION: A hash function and a service-key are stored in EEPROM 27 of a DVD player as a source. Its ID and license-key are stored in EEPROM 50 of a personal computer 2 as a sink. In a step 1, the player 1 requests the computer 2 for an ID. When it receives the supply of the ID, the player 1 applies a hash function to data (ID || service- key) that is acquired by connecting the ID and a service- key and acquires a key lk. Further, it creates a key of cryptograph sk and transmits data (e) that enciphers it with the key lk as a key to the computer 2. The computer 2 decodes the enciphered data (e) with the license- key as a key and acquires a key of cryptograph which is equal to the key sk.

公开(公告)号：JPH09186968A

公开(公告)日：1997-07-15

申请号：JP35283095

申请日：1995-12-28

Applicant: SONY CORP

Inventor： YANAGIHARA HISAFUMI ,  KOMURO TERUYOSHI ,  SHIMA HISATO

IPC: H04N5/765 ,  H04N5/781 ,  H04N5/92 ,  H04N7/24 ,  H04N19/00 ,  H04N19/423 ,  H04N19/625 ,  H04N19/70 ,  H04N19/91

Abstract: PROBLEM TO BE SOLVED: To add information denoting a change in a program of a digital broadcast in the case of reproducing plural programs continuously by a digital VTR, giving the reproduced signal to a reception and demodulator of digital broadcast in which the signal is decoded. SOLUTION: When a signal processing microcomputer 8 detects data representing a recording start position (REC START) and a recording end position (REC END) in reproduction VAUX data sent from a demultiplexer 12, the microcomputer 8 informs it to a digital interface 16. The digital interface 16 sets a discontinuous flag to identify a program change to a header of an isochronous packet to which video data sent from the demultiplexer 12 are given.

公开(公告)号：JPH0877763A

公开(公告)日：1996-03-22

申请号：JP23028694

申请日：1994-08-31

Applicant: SONY CORP

Inventor： SUGIYAMA KOICHI ,  MOTOYOSHI NOBORU ,  SHIMA HISATO ,  KOTABE NORIKO ,  SATO MAKOTO ,  TSUKAMOTO JUNICHI

IPC: H04N5/7826 ,  G11B20/00 ,  G11B27/02 ,  G11B27/024 ,  G11B31/00 ,  H04N5/765

Abstract: PURPOSE: To facilitate operations of various kinds of broadcasting mode settings by recognizing types and operations of each AV equipment forming a system and controlling them with a controller while setting addresses of them. CONSTITUTION: The controller 14 of a television receiver 1 becoming an AV center and controllers 23, 33, 43, 53, 63, and 72 of respective AV equipments 2 to 7 are bi-directionally connected with buss 9. The controller 14 recognizes where respective controllers are, what kinds of operations are possible and how signal paths are made by using addresses. Moreover, the controller 14 controls mode settings such as stereo broadcasting, bilingual broadcasting, dubbing and operations of each equipment 2 to 7. The controller 14 forms signal paths by transmitting addresses to AV equipments 2 to 7 becoming sources and to AV equipments 2 to 7 becoming destinations based on recognized contents to set respective modes. Thus, mode setting is easily performed.

公开(公告)号：JPH0818584A

公开(公告)日：1996-01-19

申请号：JP16588394

申请日：1994-06-24

Applicant: SONY CORP

Inventor： IIJIMA YUKO ,  SHIMA HISATO ,  KAWAMURA HARUMI ,  SATO MAKOTO

IPC: H04Q9/00 ,  H04L12/28 ,  H04L12/40 ,  H04L12/44

Abstract: PURPOSE:To prevent transmission reception of an information between equipments from being interrupted in the case of bus reset in the communication system connected by a P1394 serial bus. CONSTITUTION:When no AVM is in existence in a communication system, a command processing section 2 sends a command including a connection parameter registered in a CMT 4 to its own inter-equipment connection processing section 3. The inter-equipment connection processing section 3 executes the inter-equipment connection processing according to the parameter. On the other hand, when the AVM is in existence, a command including a connection parameter registered in the CMT 4 is sent to the AVM, in which the inter-equipment connection processing is left.

公开(公告)号：JPH07226022A

公开(公告)日：1995-08-22

申请号：JP4044994

申请日：1994-02-15

Applicant: SONY CORP

Inventor： SHIMA HISATO ,  ISHIMARU HIROYOSHI

IPC: G11B20/10 ,  H04J3/00 ,  H04N5/7826 ,  H04N5/919 ,  H04N9/804 ,  H04N9/806 ,  H04N9/82

Abstract: PURPOSE:To transmit a high efficiency encoding HD video signal by a circuit technique processing SD video signal. CONSTITUTION:The reproducing data of heads A1, A2 and the reproducing dad ta of the heads B1, B2 are processed by reproducing data processing circuits of respective different systems. Then, in a multiplexer and packetting circuit 17', the data outputted from two systems of shuffling circuits are time division multiplexed in synchronous block, and are constituted to a packet of a size suitable for a digital I/F. A communication error detecting parity is added to the packet by a parity generator 18, and the packet is subjected to channel coding processing by a driver 19 to be sent to a digital I/F cable.

公开(公告)号：JPH0765511A

公开(公告)日：1995-03-10

申请号：JP22797693

申请日：1993-08-20

Applicant: SONY CORP

Inventor： KUBOTA YUKIO ,  INOUE HAJIME ,  SHIMA HISATO ,  KANOTA KEIJI ,  OGURO MASAKI

IPC: G11B20/12

Abstract: PURPOSE:To record in direct the HDTV signal of almost all digital systems in the standard recording mode of a digital VTR. CONSTITUTION:One track can be set to have a format consisting of an ITI region 61, an ATV data region 62 and a subcode region 64. An application ID indicating the format consisting of the ATV data region 62 and subcode region 64 and APT are recorded in the ITI region 61, while a data format of relevant region is recorded in the application ID of each region. At the time of reproduction, it is judged from the application ID that the format is composed of the ATV data region 62 and subcode region 64 and the reproducing processing is carried out depending on the judgement. Since the ATV data is recorded in the ATV data region corresponding to combination of the audio region and video region, the HDTV signal of all digital systems can be recorded in direct.

公开(公告)号：JPH06350649A

公开(公告)日：1994-12-22

申请号：JP15623293

申请日：1993-06-02

Applicant: SONY CORP

Inventor： ISHIMARU HIROYOSHI ,  SHIMA HISATO ,  OGAWA KAZUYUKI ,  KOJIMA TAKASHI

IPC: H04L7/08 ,  H04L12/28 ,  H04L12/853 ,  H04L12/951 ,  H04N7/24 ,  H04N19/00 ,  H04N19/42 ,  H04N19/423 ,  H04N19/46 ,  H04N19/625 ,  H04N19/65 ,  H04N19/70 ,  H04N19/85 ,  H04N19/89 ,  H04L12/56 ,  H04N7/13

Abstract: PURPOSE:To make a block in the unit of blocks and a block of a packet coincident with each other and to establish frame synchronization in the system in which data in the unit of blocks are converted in packets and the packet is communicated via a channel having a communication cycle asynchronously with the period of the blocks. CONSTITUTION:Data of a track T1 are sequentially accommodated in packets DP1, DP2, ... DP26. A timing B1 of a tail end of the packet DP26 accommodating final data of the track T1 having a difference (b) from the timing of the final data is compared with a timing C1 delayed by the difference (a) between one track period and 26 communication cycles and when the timing B1 is faster than the timing C1, an idle packet is inserted next to the DP26. Furthermore, time information is sampled in the timing of a frame synchronization pulse and set to the DP1 at a sender side and the receiver side compares the time information with time information of the receiver side to generate a frame synchronization pulse.

公开(公告)号：JPH06243599A

公开(公告)日：1994-09-02

申请号：JP3229293

申请日：1993-02-22

Applicant: SONY CORP

Inventor： OGAWA KAZUYUKI ,  SHIMA HISATO ,  INOUE HAJIME ,  ISHIMARU HIROYOSHI

IPC: G11B20/12 ,  G11B20/18 ,  H03M13/00 ,  H04N5/92 ,  H04N19/42 ,  H04N19/423 ,  H04N19/426 ,  H04N19/60 ,  H04N19/65 ,  H04N19/85 ,  H04N7/133

Abstract: PURPOSE:To save the memory capacity. CONSTITUTION:The input data of a transmission format are supplied and written in the input port IN1 of a RAM 41A, and are supplied to an error detector 42A. By the error detector 42A, the error correction data of a certain data frame are outputted for a next frame interval. The error correction data and the data read out to the output port OUT1 of the RAM 41A by adjusting to the output of the error correction data are supplied to an OR circuit 43A, and the error correction data from the OR circuit 43A are supplied and written in the input port IN2 of the RAM 41A. The error correction data of respective buffering units are read out to the output port 0UT2 of the RAM 41A with 18. 1MHz clock to obtain the data of a signal processing format. The memory capacity is saved since the memory for format conversion is shared with the memory for error correction.

公开(公告)号：JPH06208777A

公开(公告)日：1994-07-26

申请号：JP32862192

申请日：1992-11-13

Applicant: SONY CORP

Inventor： OGAWA KAZUYUKI ,  SHIMA HISATO ,  KAWAMURA HARUMI ,  SAWADA TAKASHI

IPC: G11B15/07 ,  G11B23/30 ,  G11B23/40 ,  G11B23/44 ,  H04N5/78 ,  H04N5/782 ,  H04N5/7826 ,  H04N5/907

Abstract: PURPOSE:To realize high speed still picture communication by providing two types of cassettes, i.e., one cassette having a large capacity memory for storing both content information and still picture information and the other cassette having a small capacity memory for storing only the content information. CONSTITUTION:A non-volatile RAM 31 and a RAM controller 32 are built in a tape cassette 1. When the cassette 1 is loaded to a VTR 14, connecting terminals establish a communication path between a microcomputor 33 of the VTR 14 and the RAM controller 32. When a still picture display is requested, the microcomputor 33 delivers a command for reading the still picture data at high speed to the RAM controller 32 along with a start address and end address. The RAM controller 32 reads out a designated still picture data from the RAM 31 and transmits the still picture data to the VTR 14 at high communication rate. Upon finishing the communication, the RAM controller 32 returns back to low communication rate.