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    Voltage regulator for non-volatile memories implemented with low-voltage transistors
    114.
    发明公开
    Voltage regulator for non-volatile memories implemented with low-voltage transistors 有权
    SPANNUNGSREGLERFÜRNICHTFLÜCHTIGESPEICHEREINHEITEN MIT NIEDRIGSPANNUNGSTRANSISTOREN

    公开(公告)号：EP1892600A1

    公开(公告)日：2008-02-27

    申请号：EP06119456.9

    申请日：2006-08-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Campardo, Giovanni ,  Micheloni, Rino

    IPC: G05F1/56

    CPC classification number: G11C5/147 ,  G05F1/565 ,  G11C16/30

    Abstract: A voltage regulator (150I) integrated in a chip of semiconductor material is proposed. The regulator has a first input terminal for receiving a first voltage (Vhv) and an output terminal for providing a regulated voltage (Vreg) being obtained from the first voltage, the regulator including: a differential amplifier (205I) for receiving a comparison voltage (Vref) and a feedback signal (Vfb) being a function of the regulated voltage, and for proving a regulation signal (Vr) according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor (MS) having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means (Rpup) between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage (Vdd) being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors (MS1-MS5) being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means (155) for controlling the auxiliary transistors according to the regulated voltage.

    Abstract translation: 提出了集成在半导体材料芯片中的电压调节器（150I）。 调节器具有用于接收第一电压（Vhv）的第一输入端子和用于提供从第一电压获得的调节电压（Vreg）的输出端子，所述调节器包括：差分放大器（205I），用于接收比较电压 Vref）和作为调节电压的函数的反馈信号（Vfb），并且根据比较电压和反馈信号之间的比较来证明调节信号（Vr），所述差分放大器具有与 用于接收参考电压的参考端子和第二供电端子，具有用于接收调节信号的控制端子的调节晶体管（MS），以及通过第二端子和第二端子之间的负载装置（Rpup）耦合的导通第一端子和导通第二端子 参考端子和调节器的第一输入端子，调节晶体管的第二端子与输出端子耦合 ，其中所述差分放大器的第二电源端与所述调节器的第二输入端耦合，用于接收低于绝对值中的所述第一电压的第二电压（Vdd），并且其中所述调节器还包括一组 辅助晶体管（MS1-MS5）串联连接在调节晶体管的第二端子和调节器的输出端子之间，以及控制装置（155），用于根据调节电压控制辅助晶体管。

    Method and circuit for electrically programming semiconductor memory cells
    115.
    发明公开
    Method and circuit for electrically programming semiconductor memory cells 有权
    Verfahren und Vorrichtung zum elektrischen Programmieren von Halbleiterspeicherzellen

    公开(公告)号：EP1870905A1

    公开(公告)日：2007-12-26

    申请号：EP06115812.7

    申请日：2006-06-21

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Micheloni, Rino

    IPC: G11C16/34

    CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: A method of electrically programming a memory cell, comprising: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the memory cell; repeating the acts of applying and verifying until the reaching of a target programming state by the memory cell is assessed. After the reaching of a target programming state by the memory cells is assessed, at least one further electrical programming pulse is applied thereto, and the memory cell is verified at least one more time after applying the further programming pulse. In case, as a result of said further verifying, the reaching of the target programming state by the memory cell is not assessed, the method provides for applying a still further programming pulse to the memory cell.

    Abstract translation: 一种对存储器单元进行电气编程的方法，包括：向所述存储单元施加至少一个电编程脉冲; 验证存储器单元达到目标编程状态; 重复执行应用和验证的行为，直到评估存储器单元达到目标编程状态为止。 在评估存储器单元达到目标编程状态之后，向其施加至少一个另外的电编程脉冲，并且在应用另外的编程脉冲之后至少再验证存储单元。 在作为所述进一步验证的结果的情况下，未评估由存储器单元达到目标编程状态，该方法提供了将另外的编程脉冲应用于存储单元。

    Non volatile memory with detection of short circuits between word lines
    116.
    发明授权
    Non volatile memory with detection of short circuits between word lines 有权
    非易失性存储器与检测的字线之间的短路的

    公开(公告)号：EP1083575B1

    公开(公告)日：2007-11-14

    申请号：EP99830567.6

    申请日：1999-09-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Sacco, Andrea ,  Mognoni, Sabina

    IPC: G11C29/00

    CPC classification number: G11C29/50 ,  G01R31/3004 ,  G11C29/02

    Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.

    A column decoding system for semiconductor memory devices implemented with low voltage transistors
    117.
    发明公开
    A column decoding system for semiconductor memory devices implemented with low voltage transistors 有权
    Spaltendekodierungssystemfürmit Niederspannungstransistoren implementierte Halbleiterspeichervorrichtungen

    公开(公告)号：EP1845532A1

    公开(公告)日：2007-10-17

    申请号：EP06112526.6

    申请日：2006-04-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C16/24 ,  G11C7/12 ,  G11C8/10

    CPC classification number: G11C8/10 ,  G11C7/12 ,  G11C7/18 ,  G11C16/08 ,  G11C16/24 ,  G11C2207/002

    Abstract: A column decoding system (140,150) for selectively biasing bit lines (BLij) of a non-volatile memory device (100) is disclosed. The bit lines are logically grouped into at least one packet (PBL). For each packet, the column decoding system includes a plurality of selection paths each one for applying a biasing voltage to a corresponding bit line, each path including a plurality of series-connected selection transistors (Mi,Mij,Pij) each one having a threshold voltage, and selection means for selecting a path (M1,M11,P11) corresponding to a selected bit line (BL11), the selection means including means for biasing at least one transistor (P12) in each non-selected path (M1,M12,P12) to an open condition to have the corresponding non-selected bit line (BL12) floating; the selection means further includes means for biasing at least one other transistor (M12) in each non-selected path to a drop condition to introduce a voltage drop in the non-selected path higher than the threshold voltage of said one transistor (P12) in absolute value.

    Abstract translation: 公开了一种用于选择性地偏置非易失性存储器件（100）的位线（BLij）的列解码系统（140,150）。 位线被逻辑地分组成至少一个分组（PBL）。 对于每个分组，列解码系统包括多个选择路径，每个选择路径每个选择路径用于向对应的位线施加偏置电压，每个路径包括多个串联连接的选择晶体管（Mi，Mij，Pij），每个具有阈值 电压和选择装置，用于选择对应于所选位线（BL11）的路径（M1，M11，P11），所述选择装置包括用于在每个未选择路径（M1，M12）中偏置至少一个晶体管（P12）的装置 ，P12）变为打开状态，使相应的未选位线（BL12）浮置; 所述选择装置还包括用于将每个未选择的路径中的至少一个其他晶体管（M12）偏置到下降条件的装置，以将未选择的路径中的电压降高于所述一个晶体管（P12）的阈值电压 绝对值。

    Level shifter for semiconductor memory device implemented with low-voltage transistors
    118.
    发明公开
    Level shifter for semiconductor memory device implemented with low-voltage transistors 有权
    Mit Niederspannungstransistoren实施者Pegelschieberfüreine Halbleiterspeichervorrichtung

    公开(公告)号：EP1835507A1

    公开(公告)日：2007-09-19

    申请号：EP06111337.9

    申请日：2006-03-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C8/08 ,  G11C16/12 ,  G11C16/08 ,  G11C7/10 ,  H03K19/0185 ,  H03K3/356

    CPC classification number: G11C5/145 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H03K3/356113

    Abstract: A level shifter (135') is proposed. The level shifter includes a stage having a first branch (M1, M3, M5) and a second branch (M2, M4, M6), each branch including: a selection terminal for receiving a selection signal (Vp) , the selection signal received by the first branch and the second branch being alternatively at a first voltage (GND) and at a second voltage (Vdd) higher than the first voltage in absolute value, a service terminal for receiving a third voltage (POSV1) higher than the second voltage in absolute value, an input circuit ( 305) for coupling an intermediate node (IN1, IN2) to the selection terminal when at the second voltage or for insulating the intermediate node from the selection terminal otherwise, an interface circuit (310) for coupling an output terminal (OUTI, OUT2) to the intermediate node when coupled or for insulating the output terminal from the intermediate node otherwise, and an output circuit (315) for insulating the service terminal from the output terminal when coupled or for coupling the service terminal to the output terminal otherwise, the output terminals of the first branch and the second branch providing an output signal being alternatively at the second voltage or at the third voltage according to the selection signal.

    Abstract translation: 提出了一种电平移位器（135'）。 电平移位器包括具有第一分支（M1，M3，M5）和第二分支（M2，M4，M6）的级，每个分支包括：用于接收选择信号（Vp）的选择端，由 第一分支和第二分支交替地以比绝对值的第一电压高的第一电压（GND）和第二电压（Vdd），用于接收比第二电压高的绝对值的第三电压（POSV1） 绝对值，用于当处于第二电压时将中间节点（IN1，IN2）耦合到选择端子或用于将中间节点与选择终端绝缘的输入电路（305），否则，用于耦合输出的接口电路（310） 当输出端子与中间节点耦合或绝缘时，终端（OUTI，OUT2）到中间节点，否则输出端子（OUTI，OUT2）和用于将服务终端与输出端子隔离的输出电路（315） 服务终端到输出端子，否则，第一分支和第二分支的输出端子根据选择信号提供交替地处于第二电压或第三电压的输出信号。

    Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code
    119.
    发明公开
    Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code 有权
    带有嵌入式纠错码和存储器嵌入纠错代码的存储器的读出方法

    公开(公告)号：EP1830269A1

    公开(公告)日：2007-09-05

    申请号：EP06425141.6

    申请日：2006-03-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

    IPC: G06F11/10 ,  G06F11/14

    CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

    Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A 0 , A 1 , ..., A LS-1 ) to generate a first recovered string (S 1 ), and performing a first decoding attempt using the first recovered string (S 1 ). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S 2 -S N ) is generated. On the basis of a comparison between the first recovered string (S 1 ) and the second recovered string (S 2 -S N ), a modified string (S M ) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (S M ).

    Abstract translation: 用于与错误校正编码的存储器装置的读出方法设想如下步骤：执行的存储器位置处的多个第一读取（A 0，A 1，...，A LS-1），以产生一个第一回收串 （S 1），并执行使用第一回收串（S 1）的第一解码尝试。 当第一解码尝试失败，存储器位置被读取的至少一个第二时间，并且至少一个第二回收串（S 2 -S N）被产生。 在第一回收串（S 1）和所述第二回收串（S 2 -S N）之间的比较的基础上，产生一个修改后的字符串（SM），其中擦除（X）的位置，和至少一个第二 解码尝试是使用修改后的字符串（SM）。

    Method of programming an electrically programmable non-volatile semiconductor memory
    120.
    发明公开
    Method of programming an electrically programmable non-volatile semiconductor memory 审中-公开
    电可编程的非易失性半导体存储器的编程方法

    公开(公告)号：EP1426967A3

    公开(公告)日：2007-06-20

    申请号：EP03104383.9

    申请日：2003-11-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Ravasto, Roberto ,  Scommegna, Salvatrice

    IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

    Abstract: A method of programming an electrically programmable memory comprises: accessing a group of memory cells ( MC1-MCk ) of the memory to ascertain a programming state thereof ( 401,407;503,509a,513a ); applying a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state ( 405;507a,509c,513c ); and repeating said acts of accessing and applying for the memory cells in the group whose programming state is not ascertained ( 411;509b,513b ). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained ( 413,415;515 ); at least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained ( 405;507a,509c,513c ). The method guarantees that the programming state of the memory cells is ascertained in conditions that closely resembles, or are substantially identical, to the conditions in which the memory cells will be accessed in a standard read.

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