公开(公告)号：US20110272286A1

公开(公告)日：2011-11-10

申请号：US13187060

申请日：2011-07-20

Applicant: Toru NAKAI ,  Sho Akai

Inventor： Toru NAKAI ,  Sho Akai

IPC: C25D5/02 ,  C25D7/00

CPC classification number: H05K3/4644 ,  H05K3/108 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/073 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract translation: 一种制造多层印刷线路板的方法包括在第一层间树脂绝缘层上形成第一层间树脂绝缘层，第一导体电路，第二层间树脂绝缘层，第二层间树脂绝缘层中的开口部分，露出面 第一导体电路的第二层间树脂绝缘层上的无电镀膜和暴露面，以及化学镀膜上的电镀抗蚀剂。 该方法还包括用具有比无电镀膜低的离子倾向的薄膜导体层和暴露面的金属代替化学镀膜，在化学镀膜的一部分上形成包括金属的电镀膜 和薄膜导体层，剥离电镀抗蚀剂，以及除去通过剥离暴露的化学镀膜。

公开(公告)号：US20090071704A1

公开(公告)日：2009-03-19

申请号：US12284324

申请日：2008-09-19

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/465 ,  H05K1/09 ,  H05K3/184 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4661 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: A circuit board and a method for fabricating the same are disclosed. The circuit board includes: a carrier board having a circuit layer formed on at least one surface thereof; a first dielectric layer formed on the carrier board and having first openings for exposing a part of the circuit layer; conductive vias formed in the first openings; a second dielectric layer formed on the first dielectric layer and having second and third openings formed therein, wherein the second openings correspond to the first openings for exposing the conductive vias; and a multi-layered metal electroless plating circuit layer formed in the second and third openings for electrically connecting the circuit layer of the carrier board via the conductive vias, thereby allowing the multi-layered metal electroless plating circuit layer to be embedded into the first and second dielectric layers to enhance the bonding strength therebetween and increase the reliability of the circuit board and facilitate formation of fine circuits.

Abstract translation: 公开了一种电路板及其制造方法。 电路板包括：承载板，其具有形成在其至少一个表面上的电路层; 第一电介质层，形成在所述载体板上并具有用于暴露所述电路层的一部分的第一开口; 在第一开口中形成的导电通孔; 第二电介质层，形成在所述第一电介质层上并且具有形成在其中的第二和第三开口，其中所述第二开口对应于用于暴露所述导电通孔的所述第一开口; 以及形成在所述第二和第三开口中的多层金属化学镀电路层，用于经由所述导电通孔电连接所述载体板的电路层，从而允许所述多层金属化学镀电路层嵌入所述第一和第 第二电介质层，以增强它们之间的结合强度，并提高电路板的可靠性并促进精细电路的形成。

公开(公告)号：US20050269206A1

公开(公告)日：2005-12-08

申请号：US11144732

申请日：2005-06-06

Applicant: Shuichi Tanaka ,  Kazutaka Kobayashi

Inventor： Shuichi Tanaka ,  Kazutaka Kobayashi

IPC: C25D5/02 ,  H05K3/10

CPC classification number: H05K3/108 ,  H05K2201/0341 ,  H05K2203/0384 ,  H05K2203/073

Abstract: To produce a wiring substrate by employing a semi-additive method, the invention provides a production method of a wiring substrate, and a wiring substrate, that suppress the formation of undercut of an electrolytic copper plating layer during base etching and capable of ultra-fine wiring of a line/space size of 25/25 μm or below and further 10/10 μm or below. When producing a wiring substrate, the method of the invention includes the steps of applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming a wiring pattern on the surface of the electroless copper plating layer; plating metals different from copper or alloys containing at least one kind of the metals to the exposed portion to form an etching barrier plating layer; plating an etching barrier metal to form an etching barrier metal plating layer; applying electrolytic copper plating to the surface of the etching barrier metal plating layer to form wiring having a conductor layer including an electroless copper plating layer, the etching barrier metal plating layer and the electrolytic copper plating layer and the electrolytic copper plating layer; removing the resist pattern; and etching and removing the electroless copper plating layer exposed on the surface to form a wiring pattern.

Abstract translation: 为了通过使用半添加法制造布线基板，本发明提供了一种布线基板和布线基板的制造方法，其抑制在基底蚀刻期间电解铜镀层的底切形成，并能够超细 线/间距25/25 mum以下，进一步10/10 mum以下。 在制造布线基板时，本发明的方法包括以下步骤：将无电镀铜施加到由具有电绝缘性的树脂制成的基板的表面上，形成化学镀铜层; 在所述化学镀铜层的表面上施加曝光用于形成布线图案的部分的抗蚀剂图案; 将不同于铜或含有至少一种金属的合金的金属镀覆到暴露部分以形成蚀刻阻挡镀层; 电镀蚀刻阻挡金属以形成蚀刻阻挡金属镀层; 对所述蚀刻阻挡金属镀层的表面进行电解镀铜，形成具有包含无电镀铜层的导电体层，所述蚀刻阻挡金属镀层，所述电解镀铜层和所述电解镀铜层的配线; 去除抗蚀剂图案; 并蚀刻并除去暴露在表面上的化学镀铜层以形成布线图案。

公开(公告)号：US4312897A

公开(公告)日：1982-01-26

申请号：US157595

申请日：1980-06-09

Applicant: William G. Reimann

Inventor： William G. Reimann

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K3/42 ,  H05K3/18

CPC classification number: H05K3/243 ,  H05K1/0265 ,  H05K3/062 ,  H05K3/427 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0384 ,  H05K2203/0574 ,  H05K3/108 ,  H05K3/3473

Abstract: Narrow conductors and narrow spaces therebetween, typically two or three mils wide, are fabricated on outer layers of a printed wiring board with built-up areas such as plated-through holes or conductors of widths greater than two or three mils. Gold is deposited over a copper clad substrate in a pattern defining the desired circuitry. Thereafter, solder is placed at the built-up areas and, using both the solder and the gold as resist or masks, the exposed copper is removed by etching. An organic resist material is used in lieu of solder when the built-up area comprises wide conductors or leads, e.g., power busses.

Abstract translation: 典型地为2或3密耳宽的窄导体和狭窄的空间被制造在印刷线路板的外层上，其具有诸如电镀通孔或宽度大于2或3密耳的导体的组合区域。 金以限定所需电路的图案沉积在铜包覆基板上。 此后，将焊料放置在积聚区域，并且使用焊料和金作为抗蚀剂或掩模，通过蚀刻去除暴露的铜。 当组合区域包括宽导体或引线（例如功率总线）时，使用有机抗蚀剂材料代替焊料。

公开(公告)号：US4303798A

公开(公告)日：1981-12-01

申请号：US34210

申请日：1979-04-27

Applicant: Milan Paunovic

Inventor： Milan Paunovic

IPC: H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K1/09

CPC classification number: H05K3/24 ,  H05K3/244 ,  H05K3/42 ,  H05K2201/0341 ,  H05K3/062 ,  H05K3/426 ,  H05K3/427 ,  H05K3/428 ,  Y10S428/901

Abstract: The heat shock resistance of plated through holes in printed circuit assemblies is significantly increased by using as the through hole plating a special multi-layered arrangement comprising at least two layers of an electrically conductive metal in combination with at least one intermediate layer of a different electrically conductive metal. In preferred embodiments, the through hole plating comprises at least two layers of a stressed metal together with at least one intermediate layer of a metal having a stress in counteraction to that of one or more of the other metal layers. These through hole platings are capable of exposure to conditions of heat shock, such as encountered during high temperature soldering, without developing cracks resulting in breaks in the conducting pathways and failures.

Abstract translation: 通过使用特殊的多层布置，包括至少两层导电金属与至少一个不同电学中间层的组合，使用印刷电路组件中电镀通孔的耐热冲击性 导电金属。 在优选实施例中，通孔镀层包括至少两层应力金属以及至少一个金属中间层，其具有与一个或多个其它金属层的应力相反的应力。 这些通孔电镀能够暴露于热冲击的条件下，例如在高温焊接期间遇到的，而不会产生导致导电路径和故障中断的裂纹。

公开(公告)号：US11832385B2

公开(公告)日：2023-11-28

申请号：US17554101

申请日：2021-12-17

Applicant: DONGWOO FINE-CHEM CO., LTD.

Inventor： Ki Joon Park ,  Sung Jin Noh ,  Jungu Lee

IPC: H05K1/09 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L33/62 ,  H05K1/03 ,  H01L25/075

CPC classification number: H05K1/09 ,  H01L33/62 ,  H05K1/0271 ,  H01L25/075 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/18 ,  H05K2201/0326 ,  H05K2201/0341 ,  H05K2201/10106

Abstract: A circuit board includes a base layer, a seed layer formed on the base layer, and a first electrode layer formed on the seed layer. The seed layer is formed of a metal oxide with a thickness of 100 to 400 Å. The circuit board may further include an insulation layer formed on the first electrode layer and a second electrode layer formed on the insulation layer.

公开(公告)号：US20170271301A1

公开(公告)日：2017-09-21

申请号：US15593160

申请日：2017-05-11

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Sandra Louise Petty-Weeks ,  Guohao Zhang ,  Hardik Bhupendra Modi

IPC: H01L23/00 ,  H01L23/66 ,  H05K1/02 ,  H05K3/24

CPC classification number: H01L24/85 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1421 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K3/244 ,  H05K2201/0341 ,  H01L2924/00014 ,  H01L2924/00

Abstract: This disclosure relates to a radio frequency (RF) transmission line for high performance RF applications. The RF transmission line includes a bonding layer having a bonding surface and configured to receive an RF signal, a barrier layer proximate the bonding layer, a diffusion barrier layer proximate the bonding layer and configured to prevent contaminant from entering the bonding layer, and a conductive layer proximate the diffusion barrier layer. The diffusion barrier layer has a thickness that allows the received RF signal to penetrate the diffusion barrier layer to the conductive layer. The diffusion barrier layer can be a nickel layer.

公开(公告)号：US09744624B2

公开(公告)日：2017-08-29

申请号：US14742070

申请日：2015-06-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jaen-Don Lan ,  Pin-Chung Lin ,  Chen-Rui Tseng ,  Cheng-En Ho ,  Yu-An Chen

IPC: H05K3/46 ,  B23K26/402 ,  H05K3/42 ,  B23K26/382 ,  B23K103/00

CPC classification number: B23K26/402 ,  B23K26/382 ,  B23K26/389 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/30 ,  B23K2103/42 ,  B23K2103/50 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0341

Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.

公开(公告)号：US09726357B2

公开(公告)日：2017-08-08

申请号：US14761981

申请日：2014-01-20

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiro Konishi ,  Yuhsuke Fujita ,  Ippei Yamaguchi ,  Takashi Nakanishi ,  Hiroyuki Nokubo

IPC: H01L21/44 ,  H01L23/532 ,  F21V23/00 ,  F21K9/00 ,  H05K3/24 ,  H01L33/62 ,  H05K1/05 ,  F21Y115/10

CPC classification number: F21V23/002 ,  F21K9/00 ,  F21Y2115/10 ,  H01L33/62 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H05K1/053 ,  H05K3/246 ,  H05K3/247 ,  H05K2201/0341 ,  H05K2201/10106 ,  H05K2201/10409 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In a light-emitting device (30), a wiring pattern including conductor wirings (160, 165) and electrodes (170, 180) is formed on a substrate (110), and an Au layer (120) is formed on the wiring pattern.

公开(公告)号：US09661750B2

公开(公告)日：2017-05-23

申请号：US14364013

申请日：2012-11-30

Applicant: LG INNOTEK CO., LTD.

Inventor： Yun Kyoung Jo ,  Seol Hee Lim ,  Chang Hwa Park ,  Sai Ran Eom ,  Ae Rim Kim

IPC: H05K1/09 ,  H05K3/18 ,  H05K3/24

CPC classification number: H05K1/092 ,  H05K3/182 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0341 ,  H05K2201/09436 ,  H05K2201/099 ,  Y10T29/49155

Abstract: Provided is a printed circuit board, including: a circuit pattern or a base pattern formed on an insulating layer; and a plurality of metal layers formed on the circuit pattern or the base pattern, wherein the metal layers includes: a silver metal layer formed of a metal material including silver; a first palladium metal layer formed at a lower part of the silver metal layer; and a second palladium metal layer formed at an upper part of the silver metal layer.