公开(公告)号：US20170154840A1

公开(公告)日：2017-06-01

申请号：US15361144

申请日：2016-11-25

Applicant: Siyang Grande Electronics Co., Ltd.

Inventor： Yunhui Zhong

IPC: H01L23/495 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L23/49562 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L22/10 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49551 ,  H01L23/49579 ,  H01L29/861 ,  H01L2224/32245 ,  H05K3/3426 ,  H05K2201/10174 ,  H05K2201/10628 ,  H05K2201/10651

Abstract: A surface mount (SMD) diode taking a runner as the body and a manufacturing method thereof are described. An elongated runner groove is adopted to cure and package groups of diode chips arranged side by side and corresponding copper pins thereon, with the utilization rate of epoxy resin up to 90% or more. The use cost of epoxy resin is thus reduced, and environmental pollution is also reduced.

公开(公告)号：US20170135215A1

公开(公告)日：2017-05-11

申请号：US15346847

申请日：2016-11-09

Applicant: The University of Memphis Research Foundation

Inventor： Bashir I. Morshed

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K1/03 ,  H05K3/12 ,  H05K1/09 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K1/181 ,  H05K1/028 ,  H05K1/0353 ,  H05K1/0393 ,  H05K1/097 ,  H05K1/113 ,  H05K1/118 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/125 ,  H05K3/303 ,  H05K3/4007 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4664 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10106 ,  H05K2201/10143 ,  H05K2201/10151 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2203/0759 ,  H05K2203/1131

Abstract: A multilayer printed circuit as well as printed passive and active electronic components using additive printing technology is provided. The fabrication process includes a substrate and a first conductive layer that is printed with conductive ink on the substrate. An insulation layer that has uniform thickness is printed on the first conductive layer and the substrate, less via cavities, test point cavities, and a surface mount component contact point and mounting cavities. The insulation layer is replaceable with resistive layer or semi-conductive layer to fabricate electronic components. The vias are printed with conductive ink inside of the via cavities. Additionally, a second conductive layer is printed on the vias and over the insulation layer. The insulation, resistive, or semi-conducting layer, the vias, and the conductive layers are repeatedly printed in sequence to thus form the multilayer printed circuit.

公开(公告)号：US20160259139A1

公开(公告)日：2016-09-08

申请号：US15028934

申请日：2014-10-08

Applicant: AMS AG

Inventor： Jochen KRAFT ,  Karl ROHRACHER ,  Jordi TEVA

IPC: G02B6/42 ,  G02B6/13 ,  G02B6/12 ,  H01L23/48 ,  H01L31/16

CPC classification number: G02B6/4283 ,  G02B6/12002 ,  G02B6/13 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12123 ,  G02B2006/12147 ,  H01L23/481 ,  H01L23/522 ,  H01L31/16 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/0939 ,  H05K2201/09518 ,  H05K2201/09581 ,  H05K2201/10174

Abstract: The method comprises providing a semiconductor substrate, which has a main surface and an opposite further main surface, arranging a contact pad above the further main surface, forming a through-substrate via from the main surface to the further main surface at a distance from the contact pad and, by the same method step together with the through-substrate via, forming a further through-substrate via above the contact pad, arranging a hollow metal via layer in the through-substrate via and, by the same method step together with the metal via layer, arranging a further metal via layer in the further through-substrate via, the further metal via layer contacting the contact pad, and removing a bottom portion of the metal via layer to form an optical via laterally surrounded by the metal via layer.

Abstract translation: 该方法包括提供半导体衬底，其具有主表面和相对的另一个主表面，将接触焊盘布置在另一个主表面上方，从而从主表面到另一个主表面在距离 接触焊盘，并且通过与通孔基板通孔相同的方法步骤，在接触焊盘上方形成另外的通孔，在穿通基板中经由中空金属通孔层，并且通过相同的方法步骤连同 金属通孔层，在另外的通孔中经由另外的金属通孔层，通过另外的金属通孔层与接触垫接触，以及去除金属通孔层的底部，以形成由金属通孔横向包围的光学通孔 层。

公开(公告)号：US09257419B2

公开(公告)日：2016-02-09

申请号：US14216690

申请日：2014-03-17

Applicant: Weng F. Yap

Inventor： Weng F. Yap

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/12 ,  H01L25/18 ,  H01L23/00 ,  H05K1/18 ,  H05K1/02 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/24175 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10174 ,  Y10T29/41 ,  Y10T29/49126 ,  Y10T29/49139 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.

Abstract translation: 提供了用于制造系统级封装（SiP）的方法的实施例，如SiP的实施例。 在一个实施例中，该方法包括产生包括具有侧壁的第一模制封装主体的第一封装。 第一引线框架嵌入在第一模制封装主体内并且具有通过侧壁暴露的第一引线框引线。 在某些实施方案中，半导体管芯也可以封装在第一模制封装体内。 表面贴装器件（SMD）安装在第一模制封装主体的侧壁上，使得SMD的第一端子与通过侧壁暴露的第一引线框引线欧姆接触。

公开(公告)号：US20150342050A1

公开(公告)日：2015-11-26

申请号：US14761209

申请日：2014-01-15

Applicant: ARIZONA BOARD OF REGENTS ACTING FPR AND ON BEHALF OF ARIZONA STATE UNIVERSITY

Inventor： Hanqing Jiang ,  Hongyu Yu ,  Goran Konjevod ,  Yong Xu

IPC: H05K1/14 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/028 ,  H01G11/78 ,  H01M2/204 ,  H01M6/40 ,  H01M6/42 ,  H01M10/0436 ,  H01M10/0525 ,  H01M10/0583 ,  H01M10/0585 ,  H01M10/425 ,  H05K1/0272 ,  H05K1/0278 ,  H05K1/0281 ,  H05K1/0283 ,  H05K1/148 ,  H05K1/181 ,  H05K2201/046 ,  H05K2201/05 ,  H05K2201/09036 ,  H05K2201/10015 ,  H05K2201/10037 ,  H05K2201/10098 ,  H05K2201/10113 ,  H05K2201/10128 ,  H05K2201/10151 ,  H05K2201/10174 ,  H05K2203/085 ,  H05K2203/087 ,  H05K2203/09 ,  H05K2203/1184 ,  H05K2203/302

Abstract: An origami enabled manufacturing system. The system uses origami design principles to create functional materials, structures, devices and/or systems having an adjustable size and/or shape. An operational device can be coupled to a planar substrate shaped and sized to correspond to a desired origami shape of an origami pattern. A plurality of planar substrates can be coupled together by a plurality of connection members that corresponds to one or more crease of the origami pattern. An array of planar substrates can be formed that convert into a three dimensional structure with origami shape. The resulting three-dimensional structure provides smaller projection area, higher portability and deformability.

Abstract translation: 具有折纸功能的制造系统。 该系统使用折纸设计原理来创建具有可调节尺寸和/或形状的功能材料，结构，装置和/或系统。 操作装置可以耦合到形状和尺寸对应于折纸图案的期望折纸形状的平面基板。 可以通过对应于折纸图案的一个或多个折痕的多个连接构件将多个平面基板耦合在一起。 可以形成平面基板的阵列，其转换成具有折纸形状的三维结构。 所得到的三维结构提供较小的投影面积，更高的便携性和变形能力。

公开(公告)号：US09196973B2

公开(公告)日：2015-11-24

申请号：US14198960

申请日：2014-03-06

Applicant: Chicony Power Technology Co., Ltd.

Inventor： Hung-Jui Chang ,  Yu-Jen Lai

IPC: H01R9/00 ,  H01R4/48 ,  H05K1/18 ,  H05K5/00

CPC classification number: H01R4/48 ,  H01R4/70 ,  H01R12/53 ,  H02S40/34 ,  H05K1/0263 ,  H05K1/18 ,  H05K3/325 ,  H05K5/0026 ,  H05K2201/10174 ,  H05K2201/10295

Abstract: Disclosed are a solar junction box and a wire connecting structure of the solar junction box. The solar junction box includes plural first conductive tongues separately and perpendicularly plugged onto a printed circuit board, plural solar panel conducting plates combined to the first conductive tongues, and each solar panel conducting plate including an extension plate connected to a solar panel and a U-shaped snap-in plate bent and extended from the extension plate, and each U-shaped snap-in plate being snapped onto each first conductive tongue, plural insulators sheathed on the solar panel conducting plates, a pair of second conductive tongues separately and flatly attached onto a side of the printed circuit board, and two conducting terminals electrically connected to the pair of second conductive tongues. With the installation of the wire connecting structure, the volume of the solar junction box can be reduced to provide a stable electrical connection.

Abstract translation: 公开了太阳能接线盒和太阳能接线盒的导线连接结构。 太阳能接线盒包括分别并垂直地插入印刷电路板的多个第一导电舌片，与第一导电舌片组合的多个太阳能电池板导电板，并且每个太阳能电池板导电板包括连接到太阳能电池板的延伸板和U- 并且每个U形卡入板卡在每个第一导电舌片上，多个绝缘体套在太阳能电池板导电板上，一对第二导电舌片分开并平坦地连接 到印刷电路板的一侧，以及两个导电端子，电连接到该对第二导电舌片。 随着电线连接结构的安装，可以减少太阳能接线盒的体积，以提供稳定的电连接。

公开(公告)号：US20150333043A1

公开(公告)日：2015-11-19

申请号：US14640425

申请日：2015-03-06

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Koichi MASUDA

IPC: H01L25/07 ,  H05K1/18 ,  H01L25/18

CPC classification number: H01L23/488 ,  H01L24/48 ,  H01L24/49 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/10363 ,  H05K2201/10522 ,  H05K2201/1053 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207 ,  H01L2224/05599

Abstract: A first diode having a front surface anode region is mounted on a P pattern, and a second diode having a front surface cathode region is mounted on an N pattern. At this time, the first diode and the second diode are formed such that a cathode region of a front surface anode region in a first vertical relationship and an anode region of a front surface cathode region in a second vertical relationship are always located as upper portions. The front surface anode region is electrically connected to the front surface cathode region with wires provided thereover.

Abstract translation: 具有前表面阳极区域的第一二极管安装在P图案上，并且具有前表面阴极区域的第二二极管安装在N图案上。 此时，第一二极管和第二二极管被形成为使得第一垂直关系中的正面阳极区域的阴极区域和第二垂直关系的前表面阴极区域的阳极区域总是位于上部 。 前表面阳极区域通过设在其上的导电电连接到前表面阴极区域。

公开(公告)号：US20150060920A1

公开(公告)日：2015-03-05

申请号：US14459621

申请日：2014-08-14

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yasuyoshi HORIKAWA

IPC: H01L33/60 ,  H05K1/02 ,  H05K1/18 ,  H01L33/62

CPC classification number: H01L33/60 ,  H01L24/45 ,  H01L25/167 ,  H01L33/62 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0274 ,  H05K1/056 ,  H05K1/187 ,  H05K1/188 ,  H05K2201/0376 ,  H05K2201/10106 ,  H05K2201/10174 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wiring substrate includes an insulation layer, separated wires formed on a first surface of the insulation layer, a first plating layer formed on a first surface of each of the wires, a reflection layer including a first opening that exposes at least a portion of the first plating layer as a connection pad, and an electronic component mounted on a second surface of each of the wires, which is located on an opposite side of the first surface of each of the wires. The electronic component is embedded in the insulation layer.

Abstract translation: 布线基板包括绝缘层，形成在绝缘层的第一表面上的分离线，形成在每条导线的第一表面上的第一镀层，包括第一开口的反射层，该第一开口暴露至少一部分 第一电镀层作为连接焊盘，以及电子部件，其安装在每个电线的第二表面上，该电子部件位于每个电线的第一表面的相对侧上。 电子部件嵌入绝缘层。

公开(公告)号：US20150042231A1

公开(公告)日：2015-02-12

申请号：US14484880

申请日：2014-09-12

Applicant: Michael A. Tischler ,  Philippe M. Schick ,  Paul Jungwirth ,  Calvin Wade Sheen

Inventor： Michael A. Tischler ,  Philippe M. Schick ,  Paul Jungwirth ,  Calvin Wade Sheen

IPC: H05B33/08

CPC classification number: H05B33/089 ,  F21K9/20 ,  H05B33/08 ,  H05B33/0821 ,  H05K2201/09263 ,  H05K2201/10106 ,  H05K2201/10174 ,  Y10T29/49002

Abstract: In accordance with certain embodiments, an illumination system comprising a plurality of power strings features elements facilitating compensation for failure of one or more light-emitting elements connected along each power string.

Abstract translation: 根据某些实施例，包括多个功率串的照明系统具有促进对沿着每个功率线连接的一个或多个发光元件的故障进行补偿的元件。

公开(公告)号：US08860318B2

公开(公告)日：2014-10-14

申请号：US14036368

申请日：2013-09-25

Applicant: Michael A. Tischler ,  Philippe M. Schick ,  Paul Jungwirth ,  Calvin Wade Sheen

Inventor： Michael A. Tischler ,  Philippe M. Schick ,  Paul Jungwirth ,  Calvin Wade Sheen

IPC: H05B37/00 ,  H05B33/08 ,  F21K99/00

CPC classification number: H05B33/089 ,  F21K9/20 ,  H05B33/08 ,  H05B33/0821 ,  H05K2201/09263 ,  H05K2201/10106 ,  H05K2201/10174 ,  Y10T29/49002

Abstract: In accordance with certain embodiments, an illumination system comprising a plurality of power strings features elements facilitating compensation for failure of one or more light-emitting elements connected along each power string.