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    SEMICONDUCTOR MEMORY
    121.
    发明公开
    SEMICONDUCTOR MEMORY 有权
    半导体存储器

    公开(公告)号：EP2006859A9

    公开(公告)日：2009-05-20

    申请号：EP06730215.8

    申请日：2006-03-28

    Applicant: Fujitsu Microelectronics Limited

    Inventor： KOBAYASHI, Hiroyuki

    IPC: G11C29/04

    CPC classification number: G11C29/848 ,  G11C7/24

    Abstract: Regular redundancy lines are provided dedicatedly and respectively corresponding to redundancy fuse circuits in which defect addresses are programmed. A reservation redundancy line is provided in common to the redundancy fuse circuits. Address comparison circuits each compare the defect addresses programmed in the redundancy fuse circuits with an access address and output a redundancy signal when a comparison result is a match. A switch circuit is controlled to switch according to a redundancy selection signal output from a selection fuse circuit, and validates in response to the redundancy signal either a corresponding regular redundancy line or the reservation redundancy line. By dividing the redundancy lines into the regular redundancy lines and the reservation redundancy line, each of the redundancy fuse circuits can be made to correspond to one of the plurality of redundancy lines with the simple switch circuit. Therefore, a difference in propagation delay time of a signal can be made small and a difference in access time can be made small between when relieving a defect and when there is no defect.

    Abstract translation: 常规冗余线专门提供并分别对应于其中编程了缺陷地址的冗余熔丝电路。 冗余熔丝电路共同提供预留冗余线。 地址比较电路各自将冗余熔丝电路中编程的缺陷地址与访问地址进行比较，并且当比较结果匹配时输出冗余信号。 控制开关电路根据从选择熔丝电路输出的冗余选择信号进行切换，并响应于冗余信号使对应的正常冗余线或预留冗余线有效。 通过将冗余线划分为正常冗余线和预留冗余线，每个冗余熔丝电路可以通过简单的开关电路而与多条冗余线中的一条相对应。 因此，可以减小信号的传播延迟时间的差异，并且可以在减轻缺陷和没有缺陷时减小访问时间的差异。

    SEMICONDUCTOR DEVICE
    122.
    发明授权
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：EP1628399B1

    公开(公告)日：2009-05-20

    申请号：EP03730682.6

    申请日：2003-05-28

    Applicant: Fujitsu Microelectronics Limited

    Inventor： UNO, Osamu, FUJITSU VLSI LIMITED

    IPC: H03K19/00 ,  H01L27/04

    CPC classification number: H03K19/00315 ,  H03K17/0822 ,  H03K17/102

    Abstract: A semiconductor device having a terminal BUS being inputted with an applying voltage VBUS higher than a power supply voltage VDD, wherein a gate terminal G4 is applied with the power supply voltage VDD minus a threshold voltage Vthn when the voltage VBUS is lower than the power supply voltage VDD plus a threshold voltage Vthp and a PMOS transistor P4 is conducted. A gate terminal G2 is supplied with the power supply voltage VDD and a PMOS transistor P2 is turned off. When the voltage VBUS is equal to or higher than the power supply voltage VDD plus the threshold voltage Vthp, the PMOS transistor P4 is turned off by supplying the voltage VBUS to the gate terminal G4, while furthermore, a PMOS transistor P3 is conducted and the PMOS transistor P4 is turned off by supplying the voltage VBUS to the gate terminal G2. Unnecessary leak current is not fed from the terminal BUS regardless of the applying voltage VBUS and a correct voltage level can be sustained.

    Abstract translation: 一种具有端子BUS的半导体器件被输入高于电源电压VDD的施加电压VBUS，其中当电压VBUS低于电源时，栅极端子G4被施加电源电压VDD减去阈值电压Vthn 电压VDD加上阈值电压Vthp和PMOS晶体管P4。 向栅极端子G2提供电源电压VDD，并且PMOS晶体管P2截止。 当电压VBUS等于或高于电源电压VDD加上阈值电压Vthp时，通过将电压VBUS提供给栅极端子G4，PMOS晶体管P4截止，而此外，PMOS晶体管P3导通，并且 通过将电压VBUS提供给栅极端子G2来关闭PMOS晶体管P4。 不管施加电压VBUS如何，都不会从端子BUS馈送不必要的泄漏电流，并且可以维持正确的电压电平。

    Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier
    123.
    发明公开
    Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier 审中-公开
    半导体集成电路和半导体存储器件，包括过驱动读出放大器

    公开(公告)号：EP2056300A2

    公开(公告)日：2009-05-06

    申请号：EP09152393.6

    申请日：2000-02-10

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Mori, Kaoru ,  Kitamoto, Ayako ,  Matsumiya, Masato ,  Takita, Masato ,  Yamada, Shinichi ,  Nishimura, Koichi ,  Hatakeyama, Atsushi

    IPC: G11C7/08 ,  G11C11/4091 ,  G11C5/14

    CPC classification number: G11C7/08 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/065

    Abstract: A transistor (11) of a driver (5) in a semiconductor integrated circuit has its gate connected to a controlling circuit (41), and has its drain connected to a sense amplifier (AMP). The controlling circuit (41)supplies the gate of the transistor (11) with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor (11) in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor (11). Accordingly, the amplifying speed of the sense amplifier (AMP) is heightened without altering the sense amplifier (AMP) and the driver (5). Besides, the amplifying speed of the sense amplifier (AMP) is heightened without raising the power supply voltage which supplies the carriers to the driver (5).

    Abstract translation: 半导体集成电路中的驱动器（5）的晶体管（11）的栅极连接到控制电路（41），漏极连接到读出放大器（AMP）。 控制电路（41）向晶体管（11）的栅极提供超过或低于其他电源电压的栅极 - 源极电压。 与在晶体管（11）的栅极和源极之间提供电源电压的情况相比，晶体管（11）的导通状态下的漏极 - 源极电阻变得足够低。 因此，读出放大器（AMP）的放大速度被提高而不改变读出放大器（AMP）和驱动器（5）。 此外，读出放大器（AMP）的放大速度升高而不提高向驱动器（5）供应载体的电源电压。

    Prescaler circuit and buffer circuit
    124.
    发明公开
    Prescaler circuit and buffer circuit 审中-公开
    预分频电路和缓冲电路

    公开(公告)号：EP1841070A3

    公开(公告)日：2009-01-21

    申请号：EP06119268.8

    申请日：2006-08-21

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Aoki, Koju ,  Hasegawa, Katashi ,  Baba, Hiroshi

    IPC: H03K23/00 ,  H03L7/00 ,  H03F3/08

    CPC classification number: H03K21/023 ,  H03F3/2178 ,  H03F2200/333 ,  H03F2200/351 ,  H03G1/007 ,  H03L7/193

    Abstract: A prescaler that operates in a broad band. The prescaler (33) includes a buffer (41) and a counter (43). The buffer includes a first amplification circuit (50), which has three inverter circuits (52a, 52b, 52c) of different drive capacities, a second amplification circuit (54), which has four series-connected inverter circuits (54a, 54b, 54c, 54d), and a feedback circuit (55). One of the inverter circuits (52a, 52b, 52c) is connected between a capacitor (C1) and an inverter circuit (54a) via a first switch circuit (51) and a second switch circuit (53). This varies the drive capacity of the first amplification circuit (50). The feedback circuit (55) functions as a variable resistor having two transistors (T1, T2).

    Semiconductor device and method of manufacturing the same
    127.
    发明公开
    Semiconductor device and method of manufacturing the same 有权
    Halbleiterbauelement和Verfahren zu seiner Herstellung

    公开(公告)号：EP2706410A1

    公开(公告)日：2014-03-12

    申请号：EP13195857.1

    申请日：2003-02-14

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

    IPC: G03F1/26 ,  H01L23/00 ,  H01L23/58 ,  H01L21/768

    CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

    Abstract: A semiconductor device, comprising: a substrate which includes a first edge region, an integrated circuit region surrounded by the first edge region in a plan view and a second edge region located between the first edge region and the integrated circuit region in a plan view; a first interlayer insulation film (116) formed above the substrate; a contact hole formed in the first interlayer insulation film of the integrated circuit region; a first trench (131) formed in the first interlayer insulation film of the first edge region; a second trench (131), which is connected to the first trench at two positions, formed in the first interlayer insulation film of the second edge region; a second interlayer insulation film (117) formed above the first interlayer insulation film; a third trench (132), which is wider than the first trench in a plan view and which is connected to the first trench, formed in the second interlayer insulation film of the first region; a fourth trench (132), which is wider than the second trench in a plan view, which is connected to the third trench at two position in a plan view and which is connected to the second trench, formed in the second interlayer insulation film of the second region; a fifth trench formed in the second interlayer insulation film of the integrated circuit region; and a first metal film (120a) formed in the contact hole, the first trench, the second trench, the third trench, the fourth trench and the fifth trench, the first edge region includes a main-wall part (2) which includes the first trench and the third trench, and the second edge region includes a first sub-wall part (3b) which includes the second trench and the fourth trench.

    Abstract translation: 一种半导体器件，包括：在平面图中包括第一边缘区域，被所述第一边缘区域包围的集成电路区域和位于所述第一边缘区域和所述集成电路区域之间的第二边缘区域的基板; 形成在所述基板上方的第一层间绝缘膜（116） 形成在集成电路区域的第一层间绝缘膜中的接触孔; 形成在所述第一边缘区域的所述第一层间绝缘膜中的第一沟槽（131） 第二沟槽（131），其形成在所述第二边缘区域的所述第一层间绝缘膜中的两个位置处连接到所述第一沟槽; 形成在所述第一层间绝缘膜之上的第二层间绝缘膜; 第三沟槽（132），其在平面图中比所述第一沟槽宽，并且连接到所述第一沟槽，形成在所述第一区域的所述第二层间绝缘膜中; 在平面图中比第二沟槽宽的第四沟槽（132），其在平面图的两个位置处连接到第三沟槽，并且连接到形成在第二沟槽中的第二层间绝缘膜中 第二区; 形成在所述集成电路区域的第二层间绝缘膜中的第五沟槽; 以及形成在所述接触孔，所述第一沟槽，所述第二沟槽，所述第三沟槽，所述第四沟槽和所述第五沟槽中的第一金属膜（120a），所述第一边缘区域包括主壁部分（2） 第一沟槽和第三沟槽，并且第二边缘区域包括包括第二沟槽和第四沟槽的第一子壁部分（3b）。

    Phase shift mask, semiconductor device and method of manufacturing the same
    128.
    发明公开
    Phase shift mask, semiconductor device and method of manufacturing the same 审中-公开
    Phasenschiebermaske，Halbleitervorrichtung und ihr Herstellungsverfahren

    公开(公告)号：EP2503390A2

    公开(公告)日：2012-09-26

    申请号：EP12173143.4

    申请日：2003-02-14

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

    IPC: G03F1/26 ,  G03F1/32 ,  H01L23/58 ,  H01L21/768

    Abstract: A phase shift mask, comprising a phase shifter film (302) formed on a transparent substrate (300), and a light shield film (314) formed in a scribe line region (312) on said transparent substrate (300). A region surrounded by said scribe line region (312) is constituted of an integrated circuit region (304) with which an integrated circuit part is to be formed and a peripheral edge region (306) with which a peripheral edge part in a periphery of said integrated circuit part is to be formed. The light shield film (314) is further formed at least in a part of said peripheral edge region (306) and said integrated circuit region (304).

    Abstract translation: 一种相移掩模，包括形成在透明基板（300）上的移相膜（302）和形成在所述透明基板（300）上的划线区域（312）中的遮光膜（314）。 由所述划线区域（312）围绕的区域由要形成集成电路部分的集成电路区域（304）和周边边缘区域（306）构成，周边区域 集成电路部分要形成。 至少在所述周缘区域（306）和集成电路区域（304）的至少一部分中进一步形成遮光膜（314）。

    Interconnection structure in semiconductor device
    130.
    发明公开
    Interconnection structure in semiconductor device 有权
    Verbindungsstruktur在Halbleitervorrichtung

    公开(公告)号：EP2264758A2

    公开(公告)日：2010-12-22

    申请号：EP10177318.2

    申请日：2002-12-05

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Watanabe, Kenichi ,  Shimizu, Noriyoshi ,  Suzuki, Takashi

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: There is provided a semiconductor device which comprises a second insulating film (29) formed on a substantially flat surface, on which a surface of a first wiring (36) and a surface of a first insulating film (95) are continued, to cover the first wiring (36), a wiring trench (28a) formed in the second insulating film (29), connection holes (38a) formed in the second insulating film (29) to extend from the wiring trench (28a) to the first wiring (36), dummy connection holes (38b) formed in the second insulating film (29) to extend from the wiring trench (28a) to a non-forming region of the first wiring, and a second wiring (39) buried in the connection holes (38a) and the wiring trench (28a) to be connected electrically to the first wiring (36) and also buried in the dummy connection holes (38b), and formed such that a surface of the second wiring (39) and a surface of the second insulating film (29) constitute a substantially flat surface.

    Abstract translation: 提供了一种半导体器件，其包括形成在基本上平坦的表面上的第二绝缘膜（29），第一布线（36）的表面和第一绝缘膜（95）的表面在其上连续覆盖 第一布线（36），形成在第二绝缘膜（29）中的布线沟槽（28a），形成在第二绝缘膜（29）中的布线沟槽（28a）延伸到第一布线（ 36），形成在第二绝缘膜（29）中的从布线沟槽（28a）延伸到第一布线的非成形区域的虚设连接孔（38b）和埋在连接孔 （38a）和与第一布线（36）电连接并且还埋入虚拟连接孔（38b）中的布线沟槽（28a），并且形成为使得第二布线（39）的表面和 第二绝缘膜（29）构成基本平坦的表面。

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