公开(公告)号：US09331182B2

公开(公告)日：2016-05-03

申请号：US14151441

申请日：2014-01-09

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.

Abstract translation: 公开了半导体装置及其制造方法。 一方面，该方法包括在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一。 然后，在衬底上形成第二屏蔽层，并且用第二屏蔽层作为掩模形成源区和漏区中的另一个。 然后，去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。 最后，形成第一栅极电介质层，浮栅层和第二栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

公开(公告)号：US09324835B2

公开(公告)日：2016-04-26

申请号：US14430690

申请日：2012-10-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou Yin ,  Huilong Zhu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/336 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/08 ,  H01L21/266 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for manufacturing a MOSFET, including: performing ion implantation, via a shallow trench surrounding an active region in a semiconductor substrate, into a first sidewall of the active region and into a second sidewall of the active region opposite to the first sidewall to form a first heavily doped region in the first sidewall and a second heavily doped region in the second sidewall; filling the shallow trench with an insulating material, to form a shallow trench isolation; forming a gate stack and an insulating layer on the substrate, wherein the insulating layer surrounds and caps the gate stack; forming openings in the substrate using the shallow trench isolation, the first and second heavily doped regions, and the insulating layer as a hard mask; and epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a seed layer.

Abstract translation: 一种用于制造MOSFET的方法，包括：通过围绕半导体衬底中的有源区的浅沟槽进行离子注入到有源区的第一侧壁中并进入与第一侧壁相对的有源区的第二侧壁，以形成 第一侧壁中的第一重掺杂区域和第二侧壁中的第二重掺杂区域; 用绝缘材料填充浅沟槽，形成浅沟槽隔离; 在所述基板上形成栅叠层和绝缘层，其中所述绝缘层围绕并覆盖所述栅叠层; 使用浅沟槽隔离，第一和第二重掺杂区域和作为硬掩模的绝缘层在衬底中形成开口; 并且外延生长具有每个开口的底表面和侧壁的半导体层作为种子层。

公开(公告)号：US20160104801A1

公开(公告)日：2016-04-14

申请号：US14888651

申请日：2013-05-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/788 ,  H01L29/16 ,  H01L29/161 ,  G11C16/24 ,  H01L29/06 ,  H01L29/66 ,  G11C16/10 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7883 ,  G11C16/10 ,  G11C16/24 ,  H01L27/11521 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66825 ,  H01L29/7781 ,  H01L29/7848 ,  H01L29/7855

Abstract: Memory devices, methods of manufacturing the same, and methods of accessing the same are provided. In one embodiment, the memory device may include a substrate, a back gate formed on the substrate, and a transistor. The transistor may include fins formed on opposite sides of the back gate on the substrate and a gate stack formed on the substrate and intersecting the fins. The memory device may further include a back gate dielectric layer formed on side and bottom surfaces of the back gate. The back gate dielectric layer may have a thickness reduced portion at a region facing the fins on one side of the gate stack.

Abstract translation: 提供存储器件，其制造方法及其访问方法。 在一个实施例中，存储器件可以包括衬底，形成在衬底上的背栅和晶体管。 晶体管可以包括形成在衬底上的背栅极的相对侧上的鳍片和形成在衬底上并与散热片相交的栅叠层。 存储器件还可以包括形成在后栅极的侧表面和底表面上的背栅电介质层。 背栅电介质层可以在面对栅叠层一侧的散热片的区域上具有厚度减小部分。

公开(公告)号：US09312808B2

公开(公告)日：2016-04-12

申请号：US14429807

申请日：2013-03-12

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Zhiqiang Lv ,  Lan Chen

IPC: H03B5/08 ,  H03B5/02 ,  H03B5/12

CPC classification number: H03B5/02 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B2200/009

Abstract: A low-noise and big tuning range voltage-controlled oscillator. Wherein a current source circuit is used for generating working current of the voltage-controlled oscillator, a resonance circuit is used for generating an oscillating signal of the voltage-controlled oscillator, the resonance circuit is an inductance and capacitance type resonance circuit, wherein capacitance adopts a metal oxide semiconductor (MOS) capacitive reactance tube or a reverse diode to increase the tuning range of the circuit, a negative resistance circuit is used for generating negative resistance to counteract positive resistance generated by the resonance circuit, and a feedback circuit is used for feeding back the oscillating signal generated by the resonance circuit to the current source circuit to add a new current to the current source.

Abstract translation: 低噪声，大调谐范围的压控振荡器。 其中，电流源电路用于产生压控振荡器的工作电流，谐振电路用于产生压控振荡器的振荡信号，谐振电路是电感和电容型谐振电路，其中电容采用 金属氧化物半导体（MOS）电容性电抗器或反向二极管以增加电路的调谐范围，负电阻电路用于产生负电阻以抵消由谐振电路产生的正电阻，反馈电路用于 将由谐振电路产生的振荡信号反馈到电流源电路以向当前源添加新电流。

公开(公告)号：US20160086946A1

公开(公告)日：2016-03-24

申请号：US14721386

申请日：2015-05-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Hong YANG ,  Qingzhu ZHANG ,  Qiuxia XU

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0924

Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.

Abstract translation: CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域 栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层 每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。 根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能 。

公开(公告)号：US09287281B2

公开(公告)日：2016-03-15

申请号：US14403042

申请日：2013-04-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/788 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/266 ,  H01L29/10 ,  H01L29/49

CPC classification number: H01L27/11521 ,  H01L21/0257 ,  H01L21/0334 ,  H01L21/266 ,  H01L21/28273 ,  H01L29/1083 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: Flash devices and methods of manufacturing the same are provided. The device may include: a semiconductor substrate, with a well region therein; a sandwich arrangement on the well region, including a back gate conductor, semiconductor fins on opposite sides of the back gate conductor, and back gate dielectric layers separating the back gate conductor from the respective semiconductor fins, wherein the well region serves as a part of a conductive path to the back gate conductor; a front gate stack intersecting the semiconductor fins, including a floating gate dielectric layer, a floating gate conductor, a control gate dielectric layer, and a control gate conductor stacked sequentially, wherein the floating gate dielectric layer separates the floating gate conductor from the semiconductor fins; an insulating cap on top of the back gate conductor and the semiconductor fins to separate the back gate conductor from the front gate stack; and source and drain regions connected to a channel region provided by each of the semiconductor fins. The device can achieve high integration and low power consumption.

Abstract translation: 提供闪存器件及其制造方法。 该器件可以包括：其中具有阱区的半导体衬底; 在阱区域上的夹层结构，包括背栅极导体，背栅极导体的相对侧上的半导体鳍片以及将背栅极导体与相应半导体鳍片分开的背栅电介质层，其中该阱区域用作 到背栅导体的导电路径; 与所述半导体鳍片相交的前栅极堆叠，包括顺序堆叠的浮栅电介质层，浮栅导体，控制栅介质层和控制栅导体，其中所述浮栅绝缘层将所述浮栅导体与所述半导体鳍片 ; 在所述背栅导体和所述半导体鳍片的顶部上的绝缘帽，用于将所述背栅导体与所述前栅极堆叠分离; 以及连接到由每个半导体鳍片提供的沟道区域的源极和漏极区域。 该器件可实现高集成度和低功耗。

公开(公告)号：US09260297B2

公开(公告)日：2016-02-16

申请号：US14110812

申请日：2013-07-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Binbin Jiao ,  Ruiwen Liu ,  Zhigang Li ,  Yanmei Kong ,  Dapeng Chen

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/0015 ,  B81B3/0018 ,  B81B3/0051 ,  B81B3/0072 ,  B81B2203/0118

Abstract: A cantilever beam structure where stress is matched and a method of manufacturing the same are provided. An example method may comprise depositing a first sub-layer of a first material with a first deposition menu and depositing a second sub-layer of the first material with a second deposition menu different from the first deposition menu. The first sub-layer and the second sub-layer can be disposed adjacent to each other to form a first layer. The method may further comprise depositing a second layer of a second material different from the first material. The first layer and the second layer can be disposed adjacent to each other. The method may further comprise matching stress between the first layer and the second layer by adjusting at least one of thicknesses of the respective sub-layers of the first layer and a thickness of the second layer.

Abstract translation: 应力匹配的悬臂梁结构及其制造方法。 示例性方法可以包括用第一沉积菜单沉积具有第一材料的第一子层，并且用不同于第一沉积菜单的第二沉积菜单沉积第一材料的第二子层。 第一子层和第二子层可以彼此相邻地设置以形成第一层。 该方法还可以包括沉积不同于第一材料的第二材料的第二层。 第一层和第二层可以彼此相邻地设置。 该方法可以进一步包括通过调整第一层的各个子层的厚度和第二层的厚度中的至少一个来匹配第一层和第二层之间的应力。

公开(公告)号：US09252059B2

公开(公告)日：2016-02-02

申请号：US14233280

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qiuxia Xu ,  Gaobo Xu ,  Huajie Zhou ,  Huilong Zhu ,  Dapeng Chen

IPC: H01L21/8238 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/265 ,  H01L21/268 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L21/823857 ,  H01L21/0206 ,  H01L21/02301 ,  H01L21/02304 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28568 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/1066 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66575

Abstract: A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions. During activation annealing for forming the S/D regions, the dopant ions implanted in the metal gate layer diffuse and accumulate at an upper interface of the high-K gate dielectric layer to change the characteristics of the metal gates, and at a lower interface of the high-K gate dielectric layer to form electric dipoles with appropriate polarities by interfacial reaction, so as to realize adjusting of the effective work functions of the metal gates of the opposite types of MOSFETs, respectively.

Abstract translation: 一种制造半导体器件的方法，包括形成在一个半导体衬底上的两种相反类型的MOSFET，包括：为半导体衬底上的每个MOSFET限定有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在高K栅极电介质层上形成金属栅极层; 在所述金属栅极层中注入掺杂离子; 在所述金属栅极层上形成多晶硅层; 图案化多晶硅层，金属栅极层，高K栅极介电层和界面氧化物层以形成多个栅极堆叠结构; 形成围绕所述多个栅极堆叠结构中的每一个的多个栅极间隔; 以及形成多个S / D区域。 在用于形成S / D区域的激活退火期间，注入金属栅极层的掺杂剂离子在高K栅极电介质层的上界面处扩散并积聚以改变金属栅极的特性，并且在 高K栅极电介质层通过界面反应形成具有适当极性的电偶极子，以分别实现相反类型MOSFET的金属栅极的有效功函数的调整。

公开(公告)号：US20150332973A1

公开(公告)日：2015-11-19

申请号：US14652956

申请日：2013-07-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huicai ZHONG ,  Qingqing LIANG ,  Da YANG ,  Chao ZHAO

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L21/823437 ,  H01L21/26533 ,  H01L21/28176 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/78

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention.

Abstract translation: 本发明提供一种制造半导体结构的方法，其包括：a）形成沿衬底方向延伸的栅极线; b）形成覆盖半导体结构的光致抗蚀剂层; 图案化光致抗蚀剂层以在栅极线上形成开口; c）通过在开口内形成自组装共聚物来缩小开口; 以及d）经由所述开口切割所述栅极线以使所述栅极线在所述开口处绝缘。 通过在光致抗蚀剂层的开口的内壁上形成附加层，本发明提供的半导体结构的制造方法旨在减小开口方向的两个相对壁之间在栅极宽度方向上的距离，即 该方法旨在减少位于同一线路上的电隔离门的端部之间的距离，其中不需要制造线极细的切割掩模。 因此节省了工作区域，从而提高了半导体器件的集成度。 此外，本发明还提供根据本发明提供的方法的半导体结构。

公开(公告)号：US20150318354A1

公开(公告)日：2015-11-05

申请号：US14646583

申请日：2013-08-12

Applicant: INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCE

Inventor： Huaxiang Yin ,  Huilong Zhu ,  Xiaolong Ma

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/1054 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

Abstract translation: 半导体器件包括沿着第一方向在衬底上延伸的翅片; 沿着第二方向延伸穿过翅片的门; 和源极/漏极区域和在栅极的相对侧的鳍上的栅极间隔物，其中在鳍的顶部和/或侧壁上存在表面层。