公开(公告)号：JP2990118B2

公开(公告)日：1999-12-13

申请号：JP22514897

申请日：1997-08-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO INJO

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

公开(公告)号：JPH11330417A

公开(公告)日：1999-11-30

申请号：JP20805398

申请日：1998-07-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN EISHO

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To prevent a shallow PN junction between a source/drain region and a substrate from being made still thinner by a self-aligned silicide process. SOLUTION: An SEG process is carried out for forming plural amorphous silicon layers on polycrystalline silicon for various FETs and source/drain regions. A self-aligned silicide process is carried out on the layers to form titanium silicide layers 344, 346, 348 and 350, and the titanium silicide layers 344, 346, 348 and 350 are spaced from the substrate by source/drain regions. Since the formation of the titanium silicide layers 344, 346, 348 and 350 does not deplete the silicon atoms part of a substrate 300, shallow junctions causing leakage current in a DRAM device are prevented from being still thinner. In the case of a dual gate complementary metal oxide semiconductor(CMOS) structure, since the silicide layers are formed after the activation of impurities in the source/drain regions generation of mutual diffusion effect between an N-type polycrystalline silicon layer and a P-type polycrystal silicon layer can be prevented.

公开(公告)号：JPH11308089A

公开(公告)日：1999-11-05

申请号：JP18760898

申请日：1998-07-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SE KENKO ,  RYU SHUNFU ,  BAKU ANAN

IPC: H01L21/8238 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To dissolve a problem regarding an allowable range of voltages for different biased voltages by holding the difference between an output pad and gate bias of a PMOS gate transistor to be lower than the threshold voltage of the PMOS gate transistor. SOLUTION: When both a PMOS transistor 33 and an NMOS transistor 34 are turned on by a driver 32, an enable signal is set to high. Thus, an NMOS transistor 39 is turned on. When the PMOS transistor 33 and the NMOS transistor 34 are turned off by the driver 32, the enable signal is set to low. The NMOS transistor 39 is turned off and at this time, a node B is provided with the same voltage as that of a node A via a coupling resistance R. Next, a PMOS transistor 36 is turned off. In this case, a node S is held nearly at the same voltage as the voltage obtained by subtracting the threshold voltage of an NMOS transistor 35 from 3.3 volt.

公开(公告)号：JPH11307519A

公开(公告)日：1999-11-05

申请号：JP14757898

申请日：1998-05-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHANG YI-CHUN

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide an etching treatment method capable of etching treatment of a tantalum oxide layer, without changing an etching treatment station and etching agent, when a dynamic RAM is manufactured. SOLUTION: This etching treatment method is provided with a process for forming a lower electrode structure 22 of a capacitor on a semiconductor substrate 20, and a process forming sequentially a tantalum oxide layer 23, a barrier layer and a conducting layer on the lower electrode structure 22 and the substrate 20. Next by having a first reaction gas containing gas mixture composed of boron trichloride, chlorine and nitrogen (BCl2 /Cl2 /N2 ) used, a conducting layer is patterned. By the use of a second reaction gas containing a gas mixture composed of boron trichroride, chlorine and nitrogen (BCl2 /Cl2 /N2 ), the barrier layer is patterned. Finally by the use of a third reaction gas containing a gas mixture of boron trichloride, chlorine and nitrogen (BCl2 /Cl2 /N2 ), the tantalum oxide layer 23 is patterned.

公开(公告)号：JPH11260917A

公开(公告)日：1999-09-24

申请号：JP27038298

申请日：1998-09-24

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI ,  KO MASUTAMI

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a barrier layer for increasing the capability of a barrier layer for increasing adhesive strength between a low k (Low-k) dielectric layer and a barrier layer, and for preventing the diffusion of barrier layer conductive materials, and a method for manufacturing the barrier layer. SOLUTION: This is a barrier layer and a method for forming the barrier layer includes the following process. At first, a semiconductor substrate having a conductive layer already formed on this is prepared. Next, an organic low (k) dielectric layer is deposited so that the conductive layer and the semiconductor substrate can be covered. Then, an opening for exposing the conductive layer is formed in the dielectric layer. Afterwards, a first barrier layer is deposited in the opening and the surrounding area. The first barrier layer can be a silicon-containing layer or a doped silicon (doped-Si) layer formed by a plasma enhanced CVD (PECVD) method, low pressure CVD (KPCVD) method, electronic beam overprizing method, or platter method. At last, a second barrier layer is formed by covering the first barrier layer. The second barrier layer can be a titanium/titanium nitride(Ti/TiN), tungsten nitride (WN) layer, tantalum(Ta) layer, or tantalum nitride(TaN) layer.

公开(公告)号：JPH11205143A

公开(公告)日：1999-07-30

申请号：JP13237098

申请日：1998-05-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHO KUNKO

IPC: H03M1/34 ,  H03M1/42

Abstract: PROBLEM TO BE SOLVED: To convert an analog signal into a digital signal without requiring any timing signal for converting operation by feeding the respective data buts of a digital output back to a reference voltage supply circuit for determining the data but of the digital output at series of time intervals. SOLUTION: A three-bit A/D converter is provided with the array of three comparators 40-42. All the non-inverted inputs of the comparators 40-42 are mutually linked and the same analog input signal Vin to be converted into digital data is supplied. To inverted inputs 43-45 of the comparators 40-42, respectively correspondent reference voltages are supplied. The compared outputs of the comparators 40-42 are used as respective digital converted output bits Q2-Q0. The comparators 40-42 have the inverted inputs to which correspondent reference voltages Vref2 -Vref0 are supplied, respectively. These reference voltages are used by the comparators 40-42 for respectively executing comparison with the analog signal Vin.

公开(公告)号：JPH11191612A

公开(公告)日：1999-07-13

申请号：JP7378098

申请日：1998-03-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  SHA BUNEKI ,  YO BUNKAN ,  YEW TRI-RUNG

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To prevent the generation of leakage current in a capacitor by implanting a silicon layer with ions for converting it into a barrier layer and then forming a dielectric layer on the barrier layer after heat treatment and wet etching thereby, improving the quality of the dielectric layer. SOLUTION: An HSG layer 32 is formed on the surface of a conductive layer 30 using SiH4 and Si2 H6 as reaction gases, for example, and implanted with nitrogen ions. Thereafter, a thin barrier layer 34 of silicon oxynitride or silicon nitride, for example, is formed on the HSG layer 32 through rapid heating process. Since a thin native oxide layer 33 is formed on the surface of the barrier layer 34, this is removed through wet etching process. Subsequently, a dielectric layer 36 of tantalum oxide is formed on the surface of the battier layer 34 by LPCVD, followed by the formation of a top electrode layer 38 of titanium nitride on the surface of the dielectric layer 36.

公开(公告)号：JPH11163523A

公开(公告)日：1999-06-18

申请号：JP30448097

申请日：1997-11-06

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/12 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming multilayer interconnection structure, which has a landless via hole for interlayer connection and uses air as dielectric between the wirings. SOLUTION: A carbon layer is deposited on the surface of an insulator and a groove corresponding to a wiring pattern is formed on the surface of the carbon layer. A metal is supplied into the groove and onto the surface of the carbon layer, and a first layer wiring 66 is obtained by the subsequent chemical mechanical polishing process. Carbon ashing or etch back process is performed on the carbon layer, and the surface of the carbon layer is made lower than the wiring plane. An oxide capping layer 70 is formed on the wiring plane and on the surface of the recessed carbon layer. The carbon layer is consumed and removed by the oxidation process through the capping layer 70, and an air gap 74 is formed. Then, a silicon nitride etching stop layer 72 is formed on the surface of the capping layer 70, and a dielectric layer 76 is formed on the capping layer 70. After filing a via hole with a metal plug 78, a second layer wiring 80 is formed.

公开(公告)号：JPH11145383A

公开(公告)日：1999-05-28

申请号：JP29840997

申请日：1997-10-30

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method with which an integrated circuit device which can suppress the plasma damages of a gate electrode in an FET logic circuit, and at the same time, the polycrystalline silicon loss of the gate electrode can be made reduced. SOLUTION: An integrated circuit device is formed in such a way that protective layers 129 having shapes in match with that of a substrate are formed on a plurality of transfer FETs 104 and a logic FET 120, so that the film thicknesses of the layer 129 on a gate electrode 124 and source/drain regions 118 of the logic FET 120 become nearly equal to each other. Then the source/ drain regions 118 of one transfer FET 104 is exposed by forming a contact opening by removing a part of the protective layer 129, and a lower capacitor electrode 130 is formed so that the electrode 130 comes into contact with the source/drain regions 118. After the formation of the capacitor electrode 130, a charge storage capacitor with respect to the transfer FET is formed, by forming a capacitor dielectric layer 132 and an upper capacitor electrode 134 on the lower capacitor electrode 130. Thereafter, the protective layer 129 is removed from at least a part of its logic circuit region.

公开(公告)号：JPH11121616A

公开(公告)日：1999-04-30

申请号：JP27781497

申请日：1997-10-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To fill an unfilled via region, facilitate a gap filling process and prevent a void formation, by a method wherein a metal layer is deposited on wiring lines and in a gap between the wiring lines. SOLUTION: A dielectric material 40 is a silicon oxide layer or a borophosphosilicate glass layer, and a contact opening or via 44 is formed on a metal, polysilicon or an active region in a lower portion in a substrate 42. A first metal layer 46 uniformly fills the via 44 and the filled rear face is an aluminum or tungsten layer deposited so as to be flatted substantially to form a photoresist mask, and a first metal layer 46 is exposed and removed to make patterns of a wiring line. Next, an opening in the via is buried by deposition of a second metal layer to finish as a metal sidewalk spacer structure. Then, a remaining portion is extended to form a second sidewall structure to thereby prevent a void wherein contaminant accumulates from keing farmed.