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    121.
    发明专利
    未知

    公开(公告)号：IT1313847B1

    公开(公告)日：2002-09-24

    申请号：ITMI992465

    申请日：1999-11-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C8/10

    Abstract: A decoder with reduced complexity includes at least one OR circuit section and at least one AND circuit section. The at least one OR circuit section may include first and second circuit lines mutually connected and respectively receiving as inputs an address signal and an inverted address signal. The at least one AND circuit section may include first and second circuit lines which respectively receive as inputs the inverted address signal and the address signal. The at least one OR circuit section and the at least one AND circuit section may be connected to first and second booster circuits. Furthermore, the at least one OR circuit section may also include a virtual ground.

    123.
    发明专利
    未知

    公开(公告)号：ITMI20011311D0

    公开(公告)日：2001-06-21

    申请号：ITMI20011311

    申请日：2001-06-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C16/28

    Abstract: A dynamic or non-volatile memory with a differential reading system with improved load rebalancing comprising a rebalancing circuit that for values of the supply and memory selection voltage in excess of a predetermined reference voltage modifies one or the other of two currents, i.e., the measuring current or the reference current, with an equivalent effect on the load rebalancing.

    125.
    发明专利
    未知

    公开(公告)号：DE69518632T2

    公开(公告)日：2001-05-03

    申请号：DE69518632

    申请日：1995-06-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C11/413 ,  G11C8/10 ,  G11C8/00

    Abstract: A bit line selection decoder, particularly for electronic memories, comprising at least two bit lines, each of which can be selected by a respective switch, and a plurality of control lines that drive the switches. Its particularity resides in the fact that it comprises a decoder, in which the outputs drive the switches, and at least one first and one second bus of control lines that are arranged in input to the decoder and are adapted to address any one of the at least two bit lines.

    127.
    发明专利
    未知

    公开(公告)号：DE69422794T2

    公开(公告)日：2000-06-08

    申请号：DE69422794

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  PASCUCCI LUIGI

    IPC: G11C17/00 ,  G11C16/06 ,  H01L27/10 ,  H03K19/177

    Abstract: The PLA (1), which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator (30) which generates a monostable succession of read enabling signals (CPPA, CPPO, CPM) on receiving a predetermined switching edge of an external clock signal (CP). The clock generator enables evaluation of the AND (3) and OR (4) planes of the PLA and subsequently storage of the results through sections (33, 38; 48) duplicating the propagation delays of the signals in the corresponding parts (3-5) of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.

    128.
    发明专利
    未知

    公开(公告)号：DE69515991D1

    公开(公告)日：2000-05-04

    申请号：DE69515991

    申请日：1995-05-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C11/417 ,  G11C7/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0948 ,  G11C7/00 ,  G11C11/409

    Abstract: An output stage for integrated circuits, particularly for electronic memories, comprising: an input section that is adapted to acquire an input datum; a latch circuit having a first output and a second output and connected to the input section; a first inverter connected to the second output; a second inverter connected to the first output; a third inverter connected to the output of the second inverter; a grounding transistor driven by the second output of the latch circuit and adapted to connect the output of the third inverter to the ground; and a push-pull stage driven by the output of the first and third inverters. The stage according to the present invention furthermore comprises: a shorting transistor adapted to connect the output of the first inverter to the output of the second inverter; a first enabling transistor interposed between the first inverter and the first output of the latch circuit; a second enabling transistor interposed between the second inverter and the second output of the latch circuit; and a section for charging and discharging the push-pull stage, which is adapted to rapidly discharge the gate of the first transistor of the push-pull stage and to charge the gate of the second transistor of the push-pull stage during their operation.

    129.
    发明专利
    未知

    公开(公告)号：DE69319886D1

    公开(公告)日：1998-08-27

    申请号：DE69319886

    申请日：1993-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  PASCUCCI LUIGI

    IPC: G11C11/00 ,  G11C29/04 ,  G11C29/00

    Abstract: There is described a semiconductor memory comprising a matrix of lines and columns of memory cells, wherein the columns (BL) are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets (1) of columns, and there are redundancy columns (BLR) suitable for replacing a matrix column (BL) containing defective memory cells. Each of the redundancy columns (BLR) is included in a respective packet (1). The memory also comprises control circuits (5,6,7) to execute the abovementioned replacement.

    130.
    发明专利
    未知

    公开(公告)号：IT1253680B

    公开(公告)日：1995-08-22

    申请号：ITVA910027

    申请日：1991-08-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C17/18 ,  G11C8/10 ,  G11C17/12 ,  G11C

    Abstract: A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection means driven through five buses for implementing a two-level decoding, thus driving a fractionary number of rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.

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