公开(公告)号：WO2009046148A1

公开(公告)日：2009-04-09

申请号：PCT/US2008/078507

申请日：2008-10-01

Applicant: KOVIO, INC. ,  KAMATH, Arvind ,  SCHER, Erik ,  SMITH, Patrick ,  CHANDRA, Aditi ,  MOLESA, Steven

Inventor： KAMATH, Arvind ,  SCHER, Erik ,  SMITH, Patrick ,  CHANDRA, Aditi ,  MOLESA, Steven

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

Abstract translation: 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许后续沉积结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

公开(公告)号：WO03043747A8

公开(公告)日：2004-08-19

申请号：PCT/US0237175

申请日：2002-11-19

Applicant: GRAPHIC PACKAGING INT INC

Inventor： LAI LAURENCE M C ,  RUSSELL ANTHONY ,  SHAW MICHAEL J

IPC: B05D3/10 ,  B32B15/04 ,  C23F1/02 ,  C23F1/32 ,  H04R7/04 ,  H04R31/00 ,  H05K1/02 ,  H05K1/09 ,  H05K1/16 ,  H05K3/06 ,  B05D5/00 ,  B32B7/00 ,  G08B13/14 ,  H01G7/00 ,  H04R9/00

CPC classification number: H05K1/0265 ,  B32B15/04 ,  C23F1/02 ,  H04R7/04 ,  H04R31/003 ,  H05K1/09 ,  H05K1/165 ,  H05K3/06 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T428/10 ,  Y10T428/24 ,  Y10T428/24917 ,  Y10T428/31678

Abstract: To achieve a large thickness of conductive metal-containing material in a feature of a product unit processed with a liquid-based etch process, the desired thickness of material is apportioned to the two opposing surfaces of a substrate to create a two-part feature. Conventional features are made by identically patterning two same-thickness metal-containing layers and electrically connecting the resulting patterned parts in any suitable manner. However, features may also be made that do not have identical parts on opposite sides of the substrate, the two parts being electrically connected but differing in thickness, in shape, or both. Moreover, having two metal-containing layers separated by an insulator is also useful for allowing different sections of the same feature or circuit to cross one another without shorting, or to overlap in whole or in part without shorting. A polymer substrate (1004), e.g. polyethlyene terepthalate, is covered on the top and bottom surfaces by a metal- containing layer, e.g. aluminium or copper foil, which are in turn covered by etch masks (1110, 1120, 1130, 1140, 1150, 1160, 1180), e.g. a resin formed by gravure printing or photoresist. The web is immersed in a bath or sprayed with an etchant, e.g. NaOH, to form the metal- containing web (1115, 1125, 1135, 1145, 1155, 1165, 1175, 1185).

Abstract translation: 为了在用基于液体的蚀刻工艺处理的产品单元的特征中实现大厚度的含导电金属的材料，将所需的材料厚度分配给基板的两个相对的表面以产生两部分特征。 传统的特征是通过相同地构图两个相同厚度的含金属层并以任何合适的方式电连接所得到的图案化部分。 然而，也可以在衬底的相对侧上不具有相同部件的特征，两个部分电连接但是厚度，形状或两者都不同。 此外，具有由绝缘体隔开的两个含金属层也可用于允许相同特征或电路的不同部分彼此交叉而不短路，或者在不短路的情况下全部或部分重叠。 聚合物基底（1004），例如 聚对苯二甲酸乙二醇酯通过含金属层覆盖在顶表面和底表面上，例如， 铝或铜箔，其又被蚀刻掩模（1110,1120,1130,1140,1150,1160,1180）覆盖，例如。 通过凹版印刷或光致抗蚀剂形成的树脂。 将网浸入浴中或用蚀刻剂喷涂，例如， NaOH，以形成含金属网（1115,1125,1135,1145,1155,1165,1175,1185）。

公开(公告)号：WO2004062025A1

公开(公告)日：2004-07-22

申请号：PCT/US2003/038313

申请日：2003-12-03

Applicant: INTEL CORPORATION

Inventor： MA, Qing ,  HAYDEN III, Joseph ,  CHOU, Tsung-Kuan, Allen ,  TRAN, Quan

IPC: H01P3/00

CPC classification number: H01P11/003 ,  H01P3/003 ,  H05K1/0219 ,  H05K1/0237 ,  H05K3/243 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/098

Abstract: Coplanar waveguides have a center signal line and a pair of ground lines on either side formed of a sputtered material such as gold (Au). Such waveguides are subject to what is known as the edge effect at high frequency operation causing currents to concentrate and flow along adjacent edges of the lines. Providing a thicker plated layer only on adjacent edges of the lines provide substantial performance improvements over sputtered lines alone while saving significant amount of Au, thus reducing costs.

Abstract translation: 共平面波导具有中心信号线，并且由诸如金（Au）的溅射材料形成的任一侧上的一对接地线。 这种波导在高频操作下受到所谓的边缘效应的影响，导致电流集中并沿着线的相邻边缘流动。 仅在线路的相邻边缘上提供较厚的镀层，从而在单独的溅射线路上提供显着的性能改进，同时节省大量的Au，从而降低成本。

公开(公告)号：WO03096775A2

公开(公告)日：2003-11-20

申请号：PCT/US0314091

申请日：2003-05-06

Applicant: FUTURE TECHNOLOGY ,  GOTRO JEFF ,  FERNANDES KARIM

Inventor： GOTRO JEFF ,  FERNANDES KARIM

IPC: H05K3/46 ,  H05K

CPC classification number: H05K3/4626 ,  H05K2201/0195 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0759 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49155

Abstract: A multilayer circuit board comprising at least one substantially void free encapsulated heavy copper core and methods for producing such a board. Such a board may be formed by providing a first core that includes a substrate and heavy copper circuit traces, filling the spaces between circuit traces with a resin, and at least partially curing the resin so as to form two exposed and substantially planar surfaces on opposite sides of the core. The filled and planarized core is then laminated with additional dielectric layers to form a fully cured, void free multilayer printed circuit board.

Abstract translation: 包括至少一个基本上无空隙的封装重铜芯的多层电路板和用于制造这种板的方法。 这样的板可以通过提供包括基板和重铜电路迹线的第一芯体，用树脂填充电路迹线之间的空间，并且至少部分地固化树脂，从而在相对的两个表面上形成两个暴露的和基本平坦的表面 核心的一面。 然后将填充和平坦化的芯层与附加的电介质层层压以形成完全固化的无空隙的多层印刷电路板。

公开(公告)号：WO2003043747A2

公开(公告)日：2003-05-30

申请号：PCT/US2002/037175

申请日：2002-11-19

Applicant: GRAPHIC PACKAGING CORPORATION

Inventor： LAI, Laurence, M., C. ,  RUSSELL, Anthony ,  SHAW, Michael, J.

IPC: B05D5/00

CPC classification number: H05K1/0265 ,  B32B15/04 ,  C23F1/02 ,  H04R7/04 ,  H04R31/003 ,  H05K1/09 ,  H05K1/165 ,  H05K3/06 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T428/10 ,  Y10T428/24 ,  Y10T428/24917 ,  Y10T428/31678

Abstract: To achieve a large thickness of conductive metal-containing material in a feature of a product unit processed with a liquid-based etch process, the desired thickness of material is apportioned to the two opposing surfaces of a substrate to create a two-part feature. Conventional features are made by identically patterning two same-thickness metal-containing layers and electrically connecting the resulting patterned parts in any suitable manner. However, features may also be made that do not have identical parts on opposite sides of the substrate, the two parts being electrically connected but differing in thickness, in shape, or both. Moreover, having two metal-containing layers separated by an insulator is also useful for allowing different sections of the same feature or circuit to cross one another without shorting, or to overlap in whole or in part without shorting.

Abstract translation: 为了在用液基蚀刻工艺处理的产品单元的特征中实现大的厚度的含导电金属材料，将期望厚度的材料分配到基板的两个相对表面 创建一个两部分功能。 常规特征通过以相同方式图案化两个相同厚度的含金属层并且以任何合适的方式电连接所得到的图案化部分而制成。 然而，也可以做出在基板的相对侧上不具有相同部分的特征，这两个部分电连接但厚度，形状或两者不同。 此外，具有由绝缘体分开的两个含金属层也可用于允许相同特征或电路的不同部分彼此交叉而不发生短路，或者全部或部分重叠而不发生短路。

公开(公告)号：WO02041676A1

公开(公告)日：2002-05-23

申请号：PCT/ES2001/000440

申请日：2001-11-16

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/22 ,  H05K3/28

CPC classification number: H05K3/28 ,  H05K1/0263 ,  H05K3/06 ,  H05K3/22 ,  H05K2201/098 ,  H05K2203/0346 ,  H05K2203/0597

Abstract: The invention relates to a method for increasing the dielectric rigidity and insulating resistance between printed circuit board tracks. Said method involves obtaining said tracks (2) having a suitable thickness for power applications by etching a sheet of electroconductive material adhered to a dielectric sheet substrate (3) and finally coating the dielectric sheet substrate (3) and tracks (2) assembly with a protective insulating layer (4). After the tracks have been obtained (2) and before applying said protective layer (4), a step is also carried out in which the edges (5) of the tracks (2) that are formed by the intersections of their upper surfaces (6) with their side surfaces are rounded off by subsequent microetching of said edges (5). By rounding off said edges, regular thickness of the protective layer (4) of dielectric material is achieved, which increases the aforementioned dielectric rigidity and the resistance of the aluminum.

Abstract translation: 本发明涉及一种增加印刷电路板轨道之间的介电刚度和绝缘电阻的方法。 所述方法包括通过蚀刻粘附到电介质片基片（3）上的导电材料片并最终涂覆电介质片基片（3）和轨道（2）组装，获得具有适合于电力应用的厚度的所述轨道（2） 保护绝缘层（4）。 在获得轨道（2）之后并且在施加所述保护层（4）之前，还执行步骤，其中轨道（2）的由它们的上表面（6）的交叉点形成的边缘（5） ）通过随后的所述边缘（5）的微蚀刻而被倒圆。 通过使所述边缘四舍五入，实现了介电材料保护层（4）的规则厚度，这增加了上述介电刚度和铝电阻。

公开(公告)号：WO99027606A2

公开(公告)日：1999-06-03

申请号：PCT/SE1998/002092

申请日：1998-11-19

IPC: H01P3/08 ,  H01Q9/04 ,  H01Q13/20 ,  H01Q21/00 ,  H05K1/02

CPC classification number: H01P3/084 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q13/206 ,  H01Q21/0081 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2201/09972

Abstract: The invention relates to a microstrip arrangement comprising a first and a second microstrip conductor. The two microstrip conductors have essentially the same dimensions in their longitudinal direction and transverse direction, and are galvanically interconnected by means of at least one connection. The two microstrip conductors also extend essentially parallel to one another on either side of a dielectric material. As a result of this design of the microstrip arrangement, the field losses and also other influences caused by the dielectric material will be very considerably reduced, and in practice a resultant microstrip arrangement is obtained, which, with regard to its electrical performance, appears to be suspended in the air. Preferred embodiments comprise a microstrip antenna, a circuit board and a conductor application.

Abstract translation: 本发明涉及一种包括第一和第二微带导体的微带布置。 两个微带导体在其纵向和横向上具有基本上相同的尺寸，并且通过至少一个连接电流互连。 两个微带导体也在电介质材料的任一侧基本上彼此平行地延伸。 作为这种微带布置设计的结果，由介电材料引起的场损耗和其它影响将会非常显着地降低，并且在实践中获得了微结构的微结构，对于其电性能来说， 悬挂在空中。 优选实施例包括微带天线，电路板和导体应用。

公开(公告)号：WO99007194A1

公开(公告)日：1999-02-11

申请号：PCT/US1998/014434

申请日：1998-07-15

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/06

CPC classification number: H05K1/0265 ,  H05K1/111 ,  H05K3/06 ,  H05K2201/098 ,  H05K2201/10689

Abstract: An improved printed circuit (10) includes a base of a dielectric substrate (11) having an assembly of copper conductive tracks (12) formed by chemical attack made on unmasked zones a copper layer disposed over said dielectric substrate, said circuits being characterized in that the distance between centers of said tracks (12) are approximately 1.27 mm when the distance of said inter-track between the lower points of planes (12b) is approximately 0.5 mm, and the distance between the upper points of planes (12b) is approximately 0.65 mm.

Abstract translation: 一种改进的印刷电路（10）包括电介质基板（11）的基底，该基底具有通过在未掩蔽区域上形成的铜导电轨迹（12）的组件，所述铜导电轨迹（12）由布置在所述电介质基底上的铜层形成，所述电路的特征在于 当所述平面（12b）的下部点之间的所述间隙的距离为大约0.5mm，并且平面（12b）的上部点之间的距离近似时，所述轨道（12）的中心之间的距离大约为1.27mm 0.65毫米。

公开(公告)号：WO2015126629A1

公开(公告)日：2015-08-27

申请号：PCT/US2015/014537

申请日：2015-02-05

Applicant: GENERAL ELECTRIC COMPANY

Inventor： LOVELL, Alan, Carroll ,  SHEPARD, Mark, Eugene ,  MCARTHUR, Andrew, David ,  CHEN, Qin ,  GREENLEAF, Todd, David

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/46 ,  H01F17/00

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F27/24 ,  H01F27/2885 ,  H01F41/0206 ,  H01F41/043 ,  H01F41/32 ,  H01F2017/008 ,  H01F2027/2809 ,  H01F2027/2819 ,  H05K1/0224 ,  H05K1/0254 ,  H05K1/0256 ,  H05K1/144 ,  H05K1/165 ,  H05K3/46 ,  H05K2201/0715 ,  H05K2201/09672 ,  H05K2201/098 ,  Y10T29/4902 ,  Y10T29/49073

Abstract: A device includes a printed circuit board (PCB). The device may also include a high voltage coil disposed on the PCB and a low voltage coil disposed on the PCB. Further, a conductive shield forms a three-dimensional enclosure around the high voltage coil and confines an electric field generated by the device to the PCB.

Abstract translation: 一种设备包括印刷电路板（PCB）。 该装置还可以包括布置在PCB上的高压线圈和布置在PCB上的低压线圈。 此外，导电屏蔽件围绕高压线圈形成三维外壳，并将该器件产生的电场限制在PCB上。

公开(公告)号：WO2015005457A1

公开(公告)日：2015-01-15

申请号：PCT/JP2014/068511

申请日：2014-07-10

Applicant: コニカミノルタ株式会社

Inventor： 新妻　直人 ,  大屋　秀信 ,  牛久　正幸 ,  山内　正好

IPC: B05D1/26 ,  B05D5/12 ,  B05D7/00 ,  H01B5/14 ,  H05K3/10

CPC classification number: H05K3/227 ,  H01L31/1884 ,  H05K1/092 ,  H05K3/125 ,  H05K2201/0108 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2203/0545 ,  H05K2203/0783 ,  H05K2203/1105 ,  H05K2203/1173 ,  H05K2203/1581 ,  Y02E10/50

Abstract: 　細い線幅を有する細線を含むパターンを安定に形成でき、細線部のパターニング所定位置外の固形分残留を低減できる塗膜形成方法を提供することを目的とし、当該塗膜形成方法は、機能性材料を含む液体を基材１上に塗布して形成したパターン２を乾燥させることにより前記機能性材料が縁部に選択的に堆積された塗膜を形成する際に、前記液体が、前記機能性材料との親和性が高い溶剤と、前記機能性材料との親和性が低い溶剤とを含むことにより、前記機能性材料を前記塗膜の前記縁部に堆積させる。

Abstract translation: 本发明的目的是提供一种涂膜形成方法，其能够稳定地形成包括细丝宽度的细线的图案，并且能够在细线部分的规定图案化位置之外减少固体残留物。 在本发明的涂膜形成方法中，通过用包括功能材料的液体涂覆基材（1）的顶部，形成具有选择性地沉积在边缘部分上的功能材料的涂膜，以形成图案（ 2）然后干燥图案。 由于液体包括对功能材料具有高亲和力的溶剂和对功能材料具有低亲和力的溶剂，使功能材料沉积在涂膜的边缘部分上。