公开(公告)号：EP1460640A2

公开(公告)日：2004-09-22

申请号：EP04006654.0

申请日：2004-03-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Srivastavaan, Rajeev ,  Grover, Chiranjeev

IPC: G11C15/04

CPC classification number: G11C15/00

Abstract: This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match.

Abstract translation: 本发明提供了一种内容寻址存储器（CAM）架构，其通过在时钟周期的第一状态中执行互斥操作并且依赖于至少一个先前的操作在相同的第二状态中执行至少一个操作来提供改进的速度 时钟周期。 内容可寻址存储器（CAM）架构（300）包括连接到比较数据写驱动器（302）和读/写块（305）的CAM单元阵列（303），用于接收比较数据 并且分别用于在CAM单元阵列中读取和/或写入数据，所述阵列（303）的所述CAM单元的输出耦合到匹配块（304），提供匹配输出信号线，其标识匹配/ 在搜索操作结束时的不匹配，以及用于在第一状态下实现搜索和地址解码操作以及在匹配的情况下在相同时钟周期的第二状态内启用读或写操作的控制逻辑。

公开(公告)号：EP1447752A2

公开(公告)日：2004-08-18

申请号：EP04100617.2

申请日：2004-02-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Narayan, Srijib

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: The present invention provides a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements, comprising computing each butterfly of the first "log 2 P" stages on either a single processor or each of the "P" processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the "P" processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
The invention also provides a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements.

Abstract translation: 本发明提供一个可扩展的方法，用于在多处理器体系结构实现FFT / IFFT计算确实由第一“日志2 P”阶段的计算后消除了对处理器间通信的需要提供改进的吞吐量在实施使用“P”的处理元件 ，包括同时计算在任一单个处理器或每个“P”处理器的第一“日志2 P”阶段，每个阶段蝴蝶和分发寻求做各链中的“P”的处理器之间的所有后续阶段中的蝴蝶的计算 的级联蝴蝶由...组成这些蝴蝶thathave连接在一起的输入和输出，通过相同的处理器处理。 因此本发明提供一种系统，用于在多处理器体系结构获得可扩展的实施FFT / IFFT计算的那样通过在实施使用“P”消除了对处理器间通信的需要的第一个“登录2 P”阶段的计算后提供改进的吞吐量 处理元件。

公开(公告)号：EP1432126A2

公开(公告)日：2004-06-23

申请号：EP03104727.7

申请日：2003-12-16

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： BAL, Ankur ,  KHANNA, Namerita

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A high performance interconnect architecture is described that provides reduced delay minimized electromigration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

Abstract translation: 描述了一种高性能互连架构，其提供减少的延迟最小化电迁移和FPGA中的减小的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。 每组相互连接的逻辑块通过互连段链接，所述互连段通过互连层穿过中间逻辑块以直线布线，并且通过连接段选择性地连接到逻辑块。

公开(公告)号：EP1416373A2

公开(公告)日：2004-05-06

申请号：EP03024591.4

申请日：2003-10-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana ,  Verma, Jayesh

IPC: G06F7/06

CPC classification number: G06F5/10

Abstract: The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.

Abstract translation: 连接到先进先出（FIFO）存储器（301）的数据输出端的读取数据选择器（303）从奇数和偶数读指针发生器（304,305）接收选择输入。 耦合到选择器的输出端的复用器（306）选择选择器的输出作为FIFO的最终输出。 状态控制器（310）控制对最终输出的选择并输入到选择器。 还包括以下独立权利要求：（1）减少FIFO缓冲存取时间的方法; 和（2）提供FIFO缓冲器的方法。

公开(公告)号：EP1320048A3

公开(公告)日：2004-03-03

申请号：EP02027923.8

申请日：2002-12-13

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Goel, AshishKumar ,  Agarwal, Manish

IPC: G06F17/50 ,  H03K19/177

CPC classification number: G06F17/5054

Abstract: A system and method for enabling rapid partial configuration of reconfigurable devices, wherein configuration definition means define partial configuration requirements, and contain at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. Configuration loading means (300, 310, 320) provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements.

公开(公告)号：EP1330033A2

公开(公告)日：2003-07-23

申请号：EP03000105.1

申请日：2003-01-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chauhan, Rajat ,  Kaushik, Rajesh

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract translation: 本发明提供一种方法和改善的FPGA装置用于使得未使用的触发器或在IO单元和未使用的解码器或在查找表（LUT），用于核心逻辑功能的其它电路元件的其它电路元件的选择性地部署，包括断开装置 选择性地断开所述IO垫的电路或从所述LUT电路未使用的电路元件和连接装置，用于所述断开电路元件选择性地连接到要么核心逻辑的连接基质或在它们之间，以提供unabhängig配置的功能。

公开(公告)号：EP1271782A3

公开(公告)日：2003-07-23

申请号：EP02012610.8

申请日：2002-06-06

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Singh, Moninder ,  Chaudhry, Anurag

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17736

Abstract: A field programmable logic device comprising at least two independently configurable embedded memory structures wherein said memory structures differ in at least one of the following parameter memory size available configuration depths available configuration widths for efficient memory utilization.

公开(公告)号：EP1320048A2

公开(公告)日：2003-06-18

申请号：EP02027923.8

申请日：2002-12-13

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Goel, AshishKumar ,  Agarwal, Manish

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A system and method for enabling rapid partial configuration of reconfigurable devices, wherein configuration definition means define partial configuration requirements, and contain at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. Configuration loading means (300, 310, 320) provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements.

Abstract translation: 一种用于实现可重配置设备的快速部分配置的系统和方法，其中配置定义装置定义部分配置要求，并且至少包含用于部分重配置的配置数据的起始地址，指定要重新配置的连续位置的数量的数据大小，以及 对应于相邻位置的期望的配置数据。 配置加载装置（300,310,320）根据部分配置要求提供将配置数据加载到可重配置设备中。

公开(公告)号：EP3439298A1

公开(公告)日：2019-02-06

申请号：EP17188532.0

申请日：2017-08-30

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Pvt. Ltd.

Inventor： DASGUPTA, Nabarun

IPC: H04N7/20 ,  H04N21/61 ,  H03K17/12

Abstract: Satellite controller circuitry includes a connection (i.e. coaxial or single wire with ground), with a control unit (108) receiving a data message and generating a response message as output, and transmitter circuitry (110) transmitting the response message. The transmitter circuitry (110) has a first transistor having a first conduction terminal coupled to the connection (100), a second conduction terminal coupled to ground, and a control terminal coupled to receive output from the control unit (108), a second transistor having a first conduction terminal coupled to the connection (100), a second conduction terminal coupled to ground, and a control terminal coupled to receive the output from the control unit (108). The first and second transistors are configured such that a second current flowing through the first conduction terminal of the second transistor is in a non-unity ratioed relationship, or in a unity ratioed relationship, with a first current flowing through the first conduction terminal of the first transistor.

公开(公告)号：EP2804179A1

公开(公告)日：2014-11-19

申请号：EP13305644.0

申请日：2013-05-17

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics Pvt. Ltd ,  Centre National de la Recherche Scientifique ,  Université d'Aix-Marseille

Inventor： Gasiot, Gilles ,  Clerc, Sylvain ,  Yousuf, Junaid ,  Glorieux, Maximilien

IPC: G11C5/00 ,  H03K3/037 ,  H03K3/356 ,  H03L7/089

CPC classification number: H03K19/0033 ,  G11C5/005 ,  H03K3/0375 ,  H03K3/356121 ,  H03L7/08 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/095 ,  H03L7/18

Abstract: The invention concerns a circuit comprising: a data storage element (102); first and second input circuitry (104, 104') coupled respectively to first and second inputs (IN1, IN2) of the data storage element and each comprising a plurality of components adapted to generate, as a function of an initial signal (IN), first and second input signals respectively provided to said first and second inputs; wherein the data storage element comprises a first storage node and is configured such that a voltage state stored at said first storage node is protected from a change in only one of said first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on said first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on said second input signal.

Abstract translation: 本发明涉及一种电路，包括：数据存储元件（102）; 第一和第二输入电路（104,104'）分别耦合到数据存储元件的第一和第二输入（IN1，IN2），并且每个包括适于产生作为初始信号（IN）的函数的多个分量， 分别提供给所述第一和第二输入的第一和第二输入信号; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化 耦合到第一存储节点并且基于所述第一输入信号和由耦合到第一存储节点的第二晶体管的导通状态进行控制，并且基于所述第二输入信号进行控制。