公开(公告)号：WO1997021222A1

公开(公告)日：1997-06-12

申请号：PCT/US1996011790

申请日：1996-07-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAWKINS, Keith, G. ,  NAIR, Harikumar, B. ,  JAVALAGI, Shivachandra, I.

IPC: G11C07/00

CPC classification number: G11C7/1048 ,  G01R31/3185

Abstract: An integrated circuit incorporating programmable pullup and pulldown devices into each input/output (I/O) pad is described. Each I/O pad may be individually programmed to include a pullup or pulldown function. Pullpup and pulldown resistors may be removed from a system employing the present integrated circuit. Programming of the I/O pads may be accomplished in a number of ways. Following the deassertion of a reset signal, high impedance states may be transferred into a shift data storage within the integrated circuit. Once the states are received, they are shifted to the respective I/O pads through a serial chain connection of the pullup and pulldown devices within each I/O pad. The states are then maintained by each pullup and pulldown device until a subsequent reprogramming. Software programs may also reprogram the pullup and pulldown states by storing appropriate values into the shift data storage. The program then sets an appropriate value into a status register included within the integrated circuit. Upon detection of the value within the status register, the integrated circuit reprograms the high impedance states of the I/O pads with the states stored in the shift data storage.

Abstract translation: 描述了将可编程上拉和下拉器件集成到每个输入/输出（I / O）焊盘中的集成电路。 每个I / O焊盘可以被单独编程以包括上拉或下拉功能。 可以从采用本集成电路的系统中去除Pullpup和下拉电阻。 I / O焊盘的编程可以以多种方式实现。 在取消复位信号之后，高阻抗状态可以传送到集成电路内的移位数据存储器中。 一旦接收到状态，它们将通过每个I / O焊盘中的上拉和下拉器件的串行链路连接移至相应的I / O焊盘。 然后通过每个上拉和下拉装置维持状态，直到随后的重新编程。 软件程序还可以通过将适当的值存储到移位数据存储器中来重新编程上拉和下拉状态。 然后程序将一个适当的值设置到集成电路中包含的状态寄存器中。 在检测到状态寄存器中的值之后，集成电路利用存储在移位数据存储器中的状态来重新编程I / O焊盘的高阻抗状态。

公开(公告)号：WO1997018585A1

公开(公告)日：1997-05-22

申请号：PCT/US1996014340

申请日：1996-09-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  NGO, Minh, Van ,  CHAN, Darin, A.

IPC: H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/76829 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of depositing a premetal dielectric layer (110) on a semiconductor substrate (102) involves depositing of a triple premetal dielectric layer (110) in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed; the substrate is then cleaned and chemical mechanical polished.

Abstract translation: 在半导体衬底（102）上沉积金属前介电层（110）的方法包括在单一制造工具中原位沉积沉积三重金属前介电层（110），其中每个后续层在先前的层之后沉积， 没有干预的处理步骤。 因此，不执行介入的清洁步骤或其它中间步骤; 然后将基材清洗并进行化学机械抛光。

公开(公告)号：WO1997016886A2

公开(公告)日：1997-05-09

申请号：PCT/US1996014339

申请日：1996-09-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LIN, Jonathan ,  BARSAN, Radu

IPC: H03K00/00

CPC classification number: G11C16/045 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/115

Abstract: An improved control gate-addressed CMOS memory cell is provided which allows for programming and erasing by tunneling through the gate oxides of the PMOS and NMOS transistors. The CMOS memory cell (400) includes a PMOS transistor (402), an NMOS transistor (403), and an NMOS pass transistor (405). A capacitor (430) has a first terminal coupled to a common floating gate (416) of the PMOS and NMOS transistors and has a second terminal coupled to a control gate node.

Abstract translation: 提供了一种改进的控制栅极寻址CMOS存储单元，其允许通过穿过PMOS和NMOS晶体管的栅极氧化物的隧道编程和擦除。 CMOS存储单元（400）包括PMOS晶体管（402），NMOS晶体管（403）和NMOS传输晶体管（405）。 电容器（430）具有耦合到PMOS和NMOS晶体管的公共浮动栅极（416）的第一端子，并且具有耦合到控制栅极节点的第二端子。

公开(公告)号：WO1997016830A1

公开(公告)日：1997-05-09

申请号：PCT/US1996012020

申请日：1996-07-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee, E. ,  CHEN, Johnny, C.

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/28 ,  G11C16/3404

Abstract: A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.

Abstract translation: 用于闪速存储器中过度修正的参考电路包括以基本上类似于过度闪存单元的方式偏置的参考闪存单元。 参考闪存单元的泄漏电流被预设为在闪速存储器的最大工作温度下允许的泄漏电流水平，并且参考闪速存储器单元跟踪过高闪存单元的温度特性，以避免在高处过高的过高校正 温度。

公开(公告)号：WO1997016785A1

公开(公告)日：1997-05-09

申请号：PCT/US1996012019

申请日：1996-07-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TRAN, Thang, M.

IPC: G06F09/318

CPC classification number: G06F9/30185 ,  G06F9/30167 ,  G06F9/3822 ,  G06F9/3879

Abstract: A microprocessor employing a DSP unit and an instruction decode unit is provided. The instruction decode unit is configured to detect an instruction field included with an instruction, and to dispatch instructions having the instruction field to the DSP unit. The DSP unit performs DSP functions, such as a multiply-accumulate function. In one embodiment, the inclusion of an instruction prefix field in an x86 instruction indicates that the instruction is a DSP instruction. In one particular implementation, the inclusion of a segment override prefix byte within the prefix field of an x86 instruction indicates that the instruction is a DSP instruction. Embodiments of the DSP unit may include a vector memory for storing operands. A block of operands may be stored into the vector memory prior to initiating a large number of DSP operations upon the block of operands.

Abstract translation: 提供了采用DSP单元和指令解码单元的微处理器。 指令解码单元被配置为检测包括在指令中的指令字段，并且将具有指令字段的指令分派给DSP单元。 DSP单元执行DSP功能，例如乘法累加功能。 在一个实施例中，在x86指令中包括指令前缀字段指示该指令是DSP指令。 在一个特定实现中，在x86指令的前缀字段内包括段重写前缀字节指示该指令是DSP指令。 DSP单元的实施例可以包括用于存储操作数的向量存储器。 在对操作数块进行大量DSP操作之前，操作数块可以被存储到向量存储器中。

公开(公告)号：WO1997015928A1

公开(公告)日：1997-05-01

申请号：PCT/US1996010720

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee ,  CHANG, Chung, K. ,  TANG, Yuan ,  LEONG, Nancy ,  FLIESLER, Michael ,  KUO, Tiao-Hua

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.

Abstract translation: 一种包括闪存EEPROM存储单元阵列的集成电路，其中在施加每个擦除脉冲之后提供过电压校正。

公开(公告)号：WO1997015054A2

公开(公告)日：1997-04-24

申请号：PCT/US1996013930

申请日：1996-08-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TANG, Yuan

IPC: G11C00/00

CPC classification number: G11C16/3477 ,  G11C16/04 ,  G11C16/28 ,  G11C16/3468 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A memory device including an array of cells, where a reference current is generated by a predetermined number of reference cells disposed separate from the array of cells, the transconductance of such reference cells being equal to the transconductance of the cells of the array.

Abstract translation: 本发明涉及一种包括单元组件的存储器件，其中参考电流由与单元组件分开布置的确定数量的参考单元产生。 这种参考单元的跨导等于组件的单元的跨导。

公开(公告)号：WO1997013200A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015742

申请日：1996-10-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G. ,  BEN-MEIR, Amos ,  TRULL, Jeffrey, E.

IPC: G06F09/38

CPC classification number: G06F7/74 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/3812 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3853

Abstract: A scan chain (900) for sequential entries that store objects identifies an object of a first type following an object of a second type. Conceptually, if a preceding entry does not assert an "only" term, an entry storing an object of the second type generates a scan bit and asserts the "only" term which inhibits further generation of the scan bit. Each subsequent entry propagate the scan bit or if the entry stores an object of the first type, kills the scan bit and selects itself. Look-ahead logic (910, 920, 930, and 940) determines group terms from single-entry terms to indicate whether a scan bit would be generated, propagated, or killed by a group of entries. Combination of the group terms selects an entry without the delay for sequential propagation through all entries.

Abstract translation: 用于存储对象的顺序条目的扫描链（900）识别跟随第二类型的对象的第一类型的对象。 在概念上，如果前一条目不表示“唯一”术语，则存储第二类型的对象的条目生成扫描比特并且断言禁止进一步生成扫描比特的“唯一”项。 每个后续条目传播扫描位，或者如果条目存储第一种类型的对象，则会杀死扫描位并选择自身。 先行逻辑（910,920,930和940）从单条目项确定组术语，以指示扫描位是否由一组条目生成，传播或杀死。 组合术语的组合选择一个条目，而不会延迟通过所有条目进行顺序传播。

公开(公告)号：WO1997013197A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015419

申请日：1996-10-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G. ,  BEN-MEIR, Amos ,  STAPLETON, Warren, G. ,  TRULL, Jeffrey, E. ,  ROBERTS, Mark, E.

IPC: G06F09/38

CPC classification number: G06F9/30149 ,  G06F9/30174 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3853

Abstract: Scheduler logic (e.g., 434a.1, 434a.2, 434a.3, 434a.4, 434a.5, 434a.6, 434b.1, 434b.2, 434b.3, 434b.4, 434b.5, 434b.6) which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller (e.g., 403, 413, 434a, 434b) constructed in accordance with the present invention to hold younger stores until the completion of older loads (and to hold younger loads until completion of older stores). Address matching logic (510, 610) allows a load-store execution controller constructed in accordance with the present invention to avoid load-store (and store-load) dependencies. Propagate-kill scan chains (e.g., 710) supply the relative age indication of loads with respect to stores (and of stores with respect to loads).

Abstract translation: 调度器逻辑（例如，434a.1,434a.2,434a.3,434a.4,434a.5,434a.6,434b.1,434b.2,434b.3,44b.4,44b.5,448b 跟踪相对于特定负载（以及相对于特定存储器的负载）的存储器的相对年龄的.6）允许根据该存储器构造的加载存储执行控制器（例如，403,413,434a，434b） 发明要持有年轻的商店，直到年龄较大的货物完成（并持有年轻的货物，直到完成旧店）。 地址匹配逻辑（510,610）允许根据本发明构造的加载存储执行控制器避免加载存储（和存储加载）依赖性。 传播杀手扫描链（例如710）提供相对于商店（以及相对于负载的商店）的负载的相对年龄指示。

公开(公告)号：WO1997013195A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015421

申请日：1996-10-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G.

IPC: G06F09/318

CPC classification number: G06F9/382 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/324 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3853

Abstract: A ROM-based decoder exploits the high degree of redundancy between instructions to share various operation structures and substantially reduce memory size. The decoder includes a circuit which merges and shares common ROM sequences to reduce ROM size. A superscalar microprocessor includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. An instruction register is loaded with a current instruction and has various bit-fields that are updated according to the state of the processor. An entry point circuit derives an emulation ROM entry point from the instruction stored in the instruction register. The emulation ROM entry point is used to address the emulation ROM, from which an operation (Op) is read. Various fields of the Op are selectively substituted from the instruction register and emulation environment registers.

Abstract translation: 基于ROM的解码器利用指令之间的高度冗余来共享各种操作结构并大大减少存储器大小。 解码器包括合并并共享公共ROM序列以减少ROM大小的电路。 超标量微处理器包括具有仿真代码控制电路的指令解码器和模拟逻辑指令解码器的功能的仿真ROM。 指令寄存器装载有当前指令，并具有根据处理器的状态更新的各种位域。 入口点电路从存储在指令寄存器中的指令中导出仿真ROM入口点。 仿真ROM入口点用于寻址仿真ROM，从中读取操作（Op）。 Op的各个字段从指令寄存器和仿真环境寄存器中选择性地替代。