公开(公告)号：EP1265252A1

公开(公告)日：2002-12-11

申请号：EP01830369.3

申请日：2001-06-05

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Scommegna, Salvatrice

IPC: G11C16/34

CPC classification number: G11C16/344 ,  G11C16/3436

Abstract: Described herein is an erasure method for an electrically erasable nonvolatile memory device (1), in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array (3) formed by a plurality of memory cells (8) arranged in rows and columns and grouped in sectors (4) each formed by a plurality of subsectors (6), which are in turn formed by one or more rows. Erasure of the memory array (3) is performed by sectors and for each sector (4) envisages applying an erasure pulse to the gate terminals of all the memory cells (8) of the sector (4), verifying erasure of the memory cells (8) of each subsector (6), and applying a further erasure pulse to the gate terminals of the memory cells (8) of only the subsectors (6) not completely erased.

Abstract translation: 在所描述的是用于向电可擦除非易失性存储器设备（1），尤其是EEPROM-FLASH非易失性存储器件的擦除方法，其包括存储器阵列（3）通过（8）布置成行和列的存储单元的多个形成 在扇区分组（4），每个由子行业的多个形成，（6），其又通过一个或多个列构成。 存储器阵列（3）的擦除执行通过扇区和每个扇区（4）设想适用于擦除脉冲到所有的存储单元的栅极端子（8）的扇区（4）的验证的存储器单元的擦除（ 8）每个分部门（6），以及将另外的擦除脉冲施加到存储单元的栅极端子（8）仅分部门（6）未完全呼叫擦除。

公开(公告)号：EP1249842A1

公开(公告)日：2002-10-16

申请号：EP01830247.1

申请日：2001-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Gregori, Stefano ,  Micheloni, Rino ,  Pierin, Andrea ,  Khouri, Osama ,  Torelli, Guido

IPC: G11C16/12

CPC classification number: G11C11/5628 ,  G11C16/12

Abstract: Described herein is a method for programming a nonvolatile memory cell (1), which envisages applying in succession, to the gate terminal (2) of the memory cell (1), at least a first and a second programming pulse trains (F1, F2) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Advantageously, the programming method envisages applying, to the gate terminal (2) of the memory cell (1) and before the first programming pulse train (F1), also a third programming pulse train (F0; F3) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train (F1) and substantially equal to the amplitude increment in the second programming pulse train (F2), or else may be greater than the amplitude increment in the first programming pulse train (F1).

Abstract translation: 该方法涉及将相继地向存储单元的控制端子，至少两个编程脉冲串（F1，F2）与脉冲幅度在楼梯方式增加。 一个脉冲，并在第一编程脉冲串（F1）的下一个之间的幅度增量比一个脉冲，并在第二编程脉冲串（F2）的下一个之间的幅度增量越大。 从所述第一编程脉冲来训练到第二转换时当存储器单元具有与一个参考值的预先设定的关系的阈值电压。

公开(公告)号：EP1199725A1

公开(公告)日：2002-04-24

申请号：EP00830671.4

申请日：2000-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni

IPC: G11C11/56 ,  G11C8/00

CPC classification number: G11C11/5642 ,  G11C8/00 ,  G11C11/56 ,  G11C11/5621

Abstract: The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a non-binary number of bits, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

Abstract translation: 的数据管理方法适用于具有由存储单元形成的多个存储器阵列中的多级非易失性存储器设备。 每一个存储单元的存储位的非二进制数，例如三个。 以这种方式，一个字节的数据存储在存储器单元的非整数。 所述管理方法包括存储，在相同的时钟周期中，由一个字节形成的多个数据字，通过编程的相邻存储器单元的预设数目。 读书是执行了由同一个时钟周期，存储的数据字读。

公开(公告)号：EP1113450A1

公开(公告)日：2001-07-04

申请号：EP99830825.8

申请日：1999-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zammattio, Matteo ,  Motta, Ilaria ,  Micheloni, Rino ,  Golla, Carla

IPC: G11C16/30 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/145

Abstract: A voltage boost device includes a first boost stage (4) and a second boost stage (5) connected to an input terminal and to an output terminal (10), the output terminal (10) supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal (SB) having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage (4) is enabled in presence of the second logic level of the operating condition signal (SB), and is disabled in presence of the first logic level of the operating condition signal (SB); the second boost stage (5) is controlled in a first operating condition in presence of the first logic level of the operating condition signal (SB), and is controlled in a second operating condition in presence of the second logic level of the operating condition signal (SB).

Abstract translation: 升压装置包括连接到输入端和输出端（10）的第一升压级（4）和第二升压级（5），输出端（10）提供高于电源电压的输出电压。 输入端接收具有代表待机运行状态的第一逻辑电平的运行状态信号（SB）和表示主动运行状态的第二逻辑电平。 第一升压级（4）在存在操作条件信号（SB）的第二逻辑电平的情况下使能，并且在存在操作条件信号（SB）的第一逻辑电平的情况下被禁止; 在操作条件信号（SB）的第一逻辑电平存在的情况下，第二升压级（5）被控制在第一操作状态中，并且在操作状态信号的第二逻辑电平存在的情况下被控制在第二操作状态 （SB）。

公开(公告)号：EP1052572A1

公开(公告)日：2000-11-15

申请号：EP99830286.3

申请日：1999-05-12

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Manstretta, Alessandro ,  Micheloni, Rino

IPC: G06F11/20

CPC classification number: G11C29/846

Abstract: Non-volatile memory device organised with memory cells that are arranged by row and by column, comprising at least a sector of matrix cells (100), row decoders (D) and column decoders suitable to decode address signals and to activate respectively said rows or said columns, at least a sector of redundancy cells (110) such that it is possible to substitute a row of said sector of matrix cells with a row of said sector of redundancy cells. Said non-volatile memory device comprises a local column decoder (L) for said matrix sector (100) and a local column decoder (L) for said redundancy sector (110). The local column decoders (L) are controlled by external signals so that said row of said redundancy sector (110) is activated simultaneously with said row of said matrix sector (100).

Abstract translation: 具有由行和列排列的存储单元组织的非易失性存储器件，包括至少一个矩阵单元（100）的扇区，行解码器（D）和适于解码地址信号的列解码器，并分别激活所述行或 所述列，至少一个冗余单元（110）的扇区，使得可以用所述冗余单元扇区的行来代替矩阵单元的所述扇区的一行。 所述非易失性存储器件包括用于所述矩阵扇区（100）的本地列解码器（L）和用于所述冗余扇区（110）的本地列解码器（L）。 本地列解码器（L）由外部信号控制，使得所述冗余扇区（110）的所述行与所述矩阵扇区（100）的所述行同时激活。

公开(公告)号：EP1028433A1

公开(公告)日：2000-08-16

申请号：EP99830071.9

申请日：1999-02-10

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C8/14 ,  G11C11/5621 ,  G11C16/08

Abstract: The multilevel memory (50) stores words formed by a plurality of binary subwords in a plurality of cells (63a-63p), each cell having has a respective threshold value. The cells are arranged on cell rows and columns, are grouped into sectors (56) divided into sector blocks (57), and are selected via a global row decoder (51), a global column decoder (54), and a plurality of local row decoders (58), which simultaneously supply a ramp voltage (V R ) to a biasing terminal of the selected cells. Threshold reading comparators (72a, 72b) are connected to the selected cells, and generate threshold attainment signals when the ramp voltage reaches the threshold value of the selected cells; switches (65a-65d), are arranged between the global word lines (52) and local word lines (59a-59d, 60a-60d), opening of the switches is individually controlled by the threshold attainment signals, thereby the local word lines are maintained at a the threshold voltage of the respective selected cell, after opening of the switches.

Abstract translation: 多级存储器（50）在多个单元（63a-63p）中存储由多个二进制子词形成的单词，每个单元具有相应的阈值。 小区被布置在小区行和列上，被分组成划分成扇区块（57）的扇区（56），并且经由全局行解码器（51），全局列解码器（54）和多个本地 行解码器（58​​），其同时向所选择的单元的偏置端子提供斜坡电压（VR）。 阈值读取比较器（72a，72b）连接到所选择的单元，并且当斜坡电压达到所选择的单元的阈值时产生阈值读取比较器（72a，72b） 开关（65a-65d）布置在全局字线（52）和本地字线（59a-59d，60a-60d）之间，开关的开启由阈值达到信号单独控制，从而本地字线 在打开开关之后保持在相应选定单元的阈值电压。

公开(公告)号：EP0915477A1

公开(公告)日：1999-05-12

申请号：EP97830576.1

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maccarrone, Marco ,  Zammattio, Matteo

IPC: G11C8/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells.
The method consists of duplicating the ATD signal into at least one pair of signals (ATD1,ATD2) and propagating such signals through separate parallel timing chains (6,9) at the ends of which the ATD signal is reinstated, the chains (6,9) being alternately active.

Abstract translation: 本发明涉及一种方法和用于产生用于半导体集成电子存储器装置的定时存储单元读取相的脉冲同步信号（ATD）的电路。 的脉冲信号（ATD）在检测到所述存储单元的地址输入端的多个的至少一个的逻辑状态的变化的产生。 该ATD信号复制到至少一个对信号（ATD1，ATD2），并通过ATD信号纯粹是表示在其端部的分开的平行的定时链（6,9）传播搜索信号的方法besteht，所述链（6， 9）交替地处于活动状态。