公开(公告)号：US20160186327A1

公开(公告)日：2016-06-30

申请号：US14757611

申请日：2015-12-23

Applicant: Taiwan Green Point Enterprises Co., Ltd.

Inventor： Sheng-Hung Yi ,  Pen-Yi Liao

IPC: C23C18/31 ,  C23C18/16 ,  B05D1/02

CPC classification number: C23C18/31 ,  C23C18/161 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/206 ,  C23C18/30 ,  C25D5/02 ,  H05K3/182 ,  H05K3/241 ,  H05K2201/09363 ,  H05K2203/0709 ,  H05K2203/107

Abstract: A method for forming a circuit pattern on a substrate may include the steps of: providing a substrate having an insulating surface including a pattern-forming region; printing only on a portion of the insulating surface, including the pattern-forming region, with an activation ink so as to form an activation layer on the portion of the insulating surface; forming a first metal layer on the activation layer by electroless plating; and isolating a patterned portion of the first metal layer, which is formed on the pattern-forming region, from a remaining portion of the first metal layer.

Abstract translation: 在基板上形成电路图案的方法可以包括以下步骤：提供具有包括图案形成区域的绝缘表面的基板; 在绝缘表面的一部分（包括图案形成区域）上用活化油墨印刷，以在绝缘表面的部分上形成活化层; 通过化学镀在活化层上形成第一金属层; 并且从所述第一金属层的剩余部分分离形成在所述图案形成区域上的所述第一金属层的图案化部分。

公开(公告)号：US20160100479A1

公开(公告)日：2016-04-07

申请号：US14872850

申请日：2015-10-01

Applicant: E.G.O. Elektro-Geraetebau GmbH

Inventor： Micha Henrich

IPC: H05K1/02 ,  H05K1/09 ,  F21V23/00 ,  H05K1/18

CPC classification number: H05K1/0274 ,  F21V23/00 ,  H05K1/0296 ,  H05K1/09 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2201/10128 ,  H05K2201/2054 ,  Y02P70/611

Abstract: The invention relates to a display device including a printed circuit board and a number of light-emitting diodes, wherein a structured copper coating is provided on the printed circuit board. The copper coating has shielding regions which reduce or prevent penetration of light emitted downwards from the light-emitting diodes into the printed circuit board. This reduces or prevents emergence of light from the printed circuit board again at undesired locations.

Abstract translation: 本发明涉及包括印刷电路板和多个发光二极管的显示装置，其中在印刷电路板上提供结构化的铜涂层。 铜涂层具有屏蔽区域，其减少或防止从发光二极管向下发射到印刷电路板的光的穿透。 这可以在不期望的位置再次降低或防止来自印刷电路板的光的出现。

公开(公告)号：US08305767B2

公开(公告)日：2012-11-06

申请号：US11905317

申请日：2007-09-28

Applicant: Naoki Nakamura ,  Shigeru Sugino ,  Ryo Kanai

Inventor： Naoki Nakamura ,  Shigeru Sugino ,  Ryo Kanai

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H05K1/0271 ,  H05K3/28 ,  H05K3/3415 ,  H05K3/3452 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/09363 ,  H05K2201/09781 ,  H05K2203/0588 ,  H05K2203/1572 ,  Y10T29/4913 ,  Y10T29/49147

Abstract: Terminal pads are arranged on a first surface of the substrate for an electronic component to receive terminals of the electronic component. An electrically-conductive film is formed on a second surface defined on the back of the first surface over the back of a mounting area for the electronic component. The mounting area is contoured along the outer periphery of the arrangement of the terminal pads. The ratio of the area of the electrically-conductive material to the area of the surface of the substrate over the back of the mounting area is set appropriate to the ratio of the area of the electrically-conductive material to the area of the surface of the substrate over the mounting area for each electronic component. This results in suppression of flexure of the printed wiring board during reflow.

Abstract translation: 端子焊盘被布置在用于电子部件的基板的第一表面上以接收电子部件的端子。 在电子部件的安装区域的背面上的第一表面的背面上的第二表面上形成导电膜。 安装区域沿着端子焊盘的布置的外周形成轮廓。 导电材料的面积与安装区域背面的基板表面的面积的比率被设定为适合于导电材料的面积与表面的面积之比 基板在每个电子部件的安装区域上。 这导致在回流期间抑制印刷线路板的挠曲。

公开(公告)号：US20120273261A1

公开(公告)日：2012-11-01

申请号：US13547494

申请日：2012-07-12

Applicant: Sheng-Hung YI ,  Pen-Yi LIAO

Inventor： Sheng-Hung YI ,  Pen-Yi LIAO

IPC: H05K1/09 ,  H05K1/03 ,  H05K3/10 ,  H05K1/02

CPC classification number: H05K3/0026 ,  B23K26/362 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  C23C18/1603 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/2013 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  C25D5/02 ,  C25D5/54 ,  C25D7/12 ,  C25F5/00 ,  H05K3/0041 ,  H05K3/027 ,  H05K3/067 ,  H05K3/107 ,  H05K3/185 ,  H05K3/24 ,  H05K3/4661 ,  H05K2201/09036 ,  H05K2201/09363 ,  H05K2203/0392 ,  H05K2203/107 ,  Y10T29/49155

Abstract: A circuit substrate includes: an insulative substrate formed with a pattern of a recess, the recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface; a patterned metallic layer structure including at least a patterned active metal layer disposed within the recess, formed on the bottom wall surface of the recess-defining wall, and spaced apart from the surrounding wall surface of the recess-defining wall, the patterned active metal layer containing an active metal capable of initiating electroless plating; and a primary metal layer plated on the patterned metallic layer structure.

Abstract translation: 电路基板包括：形成有凹槽图案的绝缘基板，所述凹部由凹口限定壁限​​定，所述凹槽限定壁具有从所述底壁表面向上延伸的底壁表面和周围壁表面; 图案化的金属层结构，其至少包括设置在凹部内的图案化的有源金属层，形成在凹陷限定壁的底壁表面上，并且与凹陷限定壁的周围壁表面间隔开，图案化的活性金属 含有能够引发化学镀的活性金属的层; 以及镀在图案化金属层结构上的主金属层。

公开(公告)号：US08246201B2

公开(公告)日：2012-08-21

申请号：US11813857

申请日：2006-01-16

Applicant: Pierre-Alain Dumas

Inventor： Pierre-Alain Dumas

IPC: F21S4/00

CPC classification number: H05K1/18 ,  H05K1/0209 ,  H05K3/281 ,  H05K3/3447 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/062 ,  H05K2201/09363 ,  H05K2201/10106

Abstract: The invention relates to a specific printed circuit (7) comprising independent etched blocks (4) or segments in series of four such that, on a series circuit comprising five LEDs, the four blocks serve as the positioning and connection points for the welding of the pins of the LEDs, said pins being welded in an anode-to-cathode series, or the reverse depending on the direction of the current, i.e. eight electrodes in isolated blocks, such as to ensure that the connection is powered and the LEDs are fixed correctly in series of five. According to the invention, the square or rectangular blocks have a large surface (2) such that the successive holes do not tear the film of epoxy copper. In addition, said blocks are disposed along a path and a successive diagram (21) defines the symbol or pattern to be represented by the LEDs (12) which are disposed and aligned on the other decorated face of the epoxy. The incoming or outgoing bases, which supply the positive (20) or negative (3) power, or the opposite depending on the direction of the LEDs, can comprise the outgoing or incoming base that is common to other series, by means of suitable etching. The negative is always at the center of the pattern. The circuit is divided into three connection zones, A, B, C, and is powered by external contact springs. The invention is intended for the series powering of a longilineal distribution of five LEDs in series, or a multiple thereof.

Abstract translation: 本发明涉及一种特定的印刷电路（7），其包括独立的蚀刻块（4）或四个串联的段，使得在包括五个LED的串联电路上，四个块用作焊接的定位和连接点 LED的引脚，所述引脚以阳极至阴极串联焊接，或者反向取决于电流的方向，即隔离块中的八个电极，以确保连接被供电，并且LED固定 正确的五个系列。 根据本发明，正方形或矩形块具有大的表面（2），使得连续的孔不会撕裂环氧铜的膜。 此外，所述块沿着路径设置，并且连续图（21）限定由LED（12）表示的符号或图案，其被布置并对准在环氧树脂的另一装饰面上。 根据LED的方向提供正（20）或负（3）功率或相反的输入或输出基极可以通过适当的蚀刻包括其他系列共同的输出或输入基极 。 负数总是在图案的中心。 电路分为三个连接区域A，B，C，并由外部接触弹簧供电。 本发明旨在对串联的五个LED的串联分配进行串联供电，或其倍数。

公开(公告)号：US20110128100A1

公开(公告)日：2011-06-02

申请号：US12674221

申请日：2008-07-24

Applicant: Risato Ohhira

Inventor： Risato Ohhira

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/16195 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/047 ,  H01P3/08 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09363 ,  H05K2201/09618 ,  H05K2201/09663 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The high-frequency wiring board of the present invention includes: first coplanar lines provided with a first signal line and a first planar ground pattern formed on the same wiring layer as the first signal line; second coplanar lines provided with a second signal line formed on a different wiring layer than the first signal line and a second planar ground pattern formed on the same wiring layer as the second signal line; and a first ground pattern formed on the same wiring layer as the first coplanar lines. The first coplanar lines and the second coplanar lines are connected. At least the first ground pattern and the first planar ground pattern are separated in a region following the second signal line from the connection of the first signal line and the second signal line.

Abstract translation: 本发明的高频布线基板包括：第一共面线，设置有与第一信号线在同一布线层上形成的第一信号线和第一平面接地图案; 第二共面线设置有形成在与第一信号线不同的布线层上的第二信号线和形成在与第二信号线相同的布线层上的第二平面接地图案; 以及形成在与第一共面线相同的布线层上的第一接地图案​​。 第一共面线和第二共面线被连接。 至少第一接地图案​​和第一平面接地图案在第二信号线之后的区域中与第一信号线和第二信号线的连接分开。

公开(公告)号：US20110103058A1

公开(公告)日：2011-05-05

申请号：US11813857

申请日：2006-01-16

Applicant: Pierre-Alain Dumas

Inventor： Pierre-Alain Dumas

IPC: F21S4/00

CPC classification number: H05K1/18 ,  H05K1/0209 ,  H05K3/281 ,  H05K3/3447 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/062 ,  H05K2201/09363 ,  H05K2201/10106

Abstract: The invention relates to a specific printed circuit (7) comprising independent etched blocks (4) or segments in series of four such that, on a series circuit comprising five LEDs, the four blocks serve as the positioning and connection points for the welding of the pins of the LEDs, said pins being welded in an anode-to-cathode series, or the reverse depending on the direction of the current, i.e. eight electrodes in isolated blocks, such as to ensure that the connection is powered and the LEDs are fixed correctly in series of five. According to the invention, the square or rectangular blocks have a large surface (2) such that the successive holes do not tear the film of epoxy copper. In addition, said blocks are disposed along a path and a successive diagram (21) defines the symbol or pattern to be represented by the LEDs (12) which are disposed and aligned on the other decorated face of the epoxy. The incoming or outgoing bases, which supply the positive (20) or negative (3) power, or the opposite depending on the direction of the LEDs, can comprise the outgoing or incoming base that is common to other series, by means of suitable etching. The negative is always at the centre of the pattern. The circuit is divided into three connection zones, A, B, C, and is powered by external contact springs. The invention is intended for the series powering of a longilineal distribution of five LEDs in series, or a multiple thereof.

Abstract translation: 本发明涉及一种特定的印刷电路（7），其包括独立的蚀刻块（4）或四个串联的段，使得在包括五个LED的串联电路上，四个块用作焊接的定位和连接点 LED的引脚，所述引脚以阳极至阴极串联焊接，或者反向取决于电流的方向，即隔离块中的八个电极，以确保连接被供电并且LED固定 正确的五个系列。 根据本发明，正方形或矩形块具有大的表面（2），使得连续的孔不会撕裂环氧铜的膜。 此外，所述块沿着路径设置，并且连续图（21）限定由LED（12）表示的符号或图案，其被布置并对准在环氧树脂的另一装饰面上。 根据LED的方向提供正（20）或负（3）功率或相反的输入或输出基极可以通过适当的蚀刻包括其他系列共同的输出或输入基极 。 负数总是在图案的中心。 电路分为三个连接区域A，B，C，并由外部接触弹簧供电。 本发明旨在对串联的五个LED的串联分配进行串联供电，或其倍数。

公开(公告)号：US07821115B2

公开(公告)日：2010-10-26

申请号：US11566892

申请日：2006-12-05

Applicant: Chihiro Sasaki ,  Yasuaki Iwata

Inventor： Chihiro Sasaki ,  Yasuaki Iwata

IPC: H01L23/495 ,  H01L21/00 ,  H01R9/00

CPC classification number: H01L23/4985 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K1/189 ,  H05K2201/09363 ,  H05K2201/09781 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.

Abstract translation: 如提供的，具有改善的散热性的带载体封装上的半导体器件。 为了实现多通道配置，已经增加了半导体器件的输出数量，并且采用更窄的间距。 包括形成在其基带28上的引线图案21至24以及安装在带载体20上并具有布置在其上的电极图案11至14的半导体器件10的带状载体20。 半导体装置10在散热电极图案15〜17不与电极图案11〜14不干涉的位置包括散热电极图案15〜17。引线图案21〜24电连接到对应的电极图案11〜 14。 在载带20上形成散热图案25〜27。 散热图案的表面积比引线图案宽，并且散热电极图案设置在其上。

公开(公告)号：US07749813B2

公开(公告)日：2010-07-06

申请号：US12038200

申请日：2008-02-27

Applicant: Boris Kolodin ,  James Reginelli

Inventor： Boris Kolodin ,  James Reginelli

IPC: H01L21/00 ,  H01L23/12 ,  H01L23/053 ,  H05K1/00 ,  H05K3/02 ,  H05K3/10

CPC classification number: H01L25/0753 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01079 ,  H05K3/027 ,  H05K3/064 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a laser-cut gap formed by the laser cutting; and bonding a light emitting diode (LED) chip to the circuit board across or adjacent to the laser-cut gap, the bonding including operatively electrically connecting an electrode of the LED chip to one of the sub-traces without using an interposed submount. A semiconductor package comprises an LED chip flip-chip bonded to sub-traces of an electrically conductive trace of a circuit board, the sub-traces being electrically isolated from each other by a narrow gap of less than or about 100 microns.

Abstract translation: 封装方法包括：通过在绝缘板上形成基本上连续的导电层形成电路板，并移除所述连续导电层的选定部分以限定导电迹线; 激光切割导电迹线以通过激光切割形成的激光切割间隙来彼此电隔离的子迹线; 以及将发光二极管（LED）芯片连接到所述激光切割间隙上或与所述激光切割间隙相邻的所述电路板，所述接合包括在不使用插入的基座的情况下将所述LED芯片的电极可操作地电连接到所述子迹线之一。 半导体封装包括结合到电路板的导电迹线的子迹线的LED芯片倒装芯片，子迹线通过小于或约100微米的窄间隙彼此电隔离。

公开(公告)号：US07710045B2

公开(公告)日：2010-05-04

申请号：US11276901

申请日：2006-03-17

Applicant: John C. Schultz ,  Nelson B. O'Bryan

Inventor： John C. Schultz ,  Nelson B. O'Bryan

IPC: H05B41/16

CPC classification number: H05K1/0204 ,  F21K9/00 ,  G02F2001/133628 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/0209 ,  H05K1/0373 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/0209 ,  H05K2201/09318 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2203/1189 ,  H01L2924/00 ,  H01L2224/4554

Abstract: Illumination assemblies include a substrate having a first and second electrically conductive layer separated by an electrically insulating layer. The insulating layer includes a polymer material loaded with thermally conductive particles. At least a portion of the thermally conductive particles simultaneously contact both the first and second electrically conductive layers. A plurality of light sources such as LEDs or other miniature light sources are preferably disposed on the first conductive layer.

Abstract translation: 照明组件包括具有由电绝缘层分隔开的第一和第二导电层的衬底。 绝缘层包括装载有导热颗粒的聚合物材料。 至少一部分导热颗粒同时接触第一和第二导电层。 诸如LED或其它微型光源的多个光源优选设置在第一导电层上。