公开(公告)号：DE69131390D1

公开(公告)日：1999-08-05

申请号：DE69131390

申请日：1991-04-11

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions of high dopant concentration defined after growth of a first epitaxial layer.

公开(公告)号：ITMI980170A1

公开(公告)日：1999-07-30

申请号：ITMI980170

申请日：1998-01-30

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PATTI DAVIDE ,  PRIOLO FRANCESCO ,  PRIVITERA VITTORIO ,  FRANZO' GIORGIA

IPC: H01L21/8234 ,  H01L29/08

Abstract: An electronic power device is integrated on a semiconductor substrate having a first conductivity type, on which an epitaxial layer of the same conductivity type is grown. The power device comprises a power stage and a control stage, this latter enclosed in an isolated region having a second conductivity type. The power stage comprises a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The control stage comprises a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage and the control stage to be entirely formed in the epitaxial layer.

公开(公告)号：DE69324003T2

公开(公告)日：1999-07-15

申请号：DE69324003

申请日：1993-06-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  COFFA SALVATORE

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/167 ,  H01L29/73 ,  H01L29/732

Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate (1) of the N type over which a lightly doped N type layer (2), constituting a collector region of the transistor, is superimposed; the transistor has a base region comprising a heavily doped P type diffusion (4) which extends into the lightly doped N type layer (2) from a top surface, and an emitter region constituted by a heavily doped N type diffusion (11) extending from said top surface within said heavily doped P type diffusion (4); the heavily doped P type diffusion (4) is obtained within a deep lightly doped P type diffusion (3), extending from said top surface into the lightly doped N type layer (2) and formed with acceptor impurities represented by atoms of aluminium.

公开(公告)号：DE69321965T2

公开(公告)日：1999-06-02

申请号：DE69321965

申请日：1993-12-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： RONSISVALLE CESARE

IPC: H01L21/52 ,  H01L23/051 ,  H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

公开(公告)号：DE69418037D1

公开(公告)日：1999-05-27

申请号：DE69418037

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L21/60 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L29/72

Abstract: In a MOS-technology power device chip and package assembly, the MOS-technology power device chip (1) comprises a semiconductor material layer (4,5) in which a plurality of elementary functional units (6) is integrated, each elementary functional unit (6) contributing for a respective fraction to an overall current and comprising a first doped region (7) of a first conductivity type formed in said semiconductor layer (4,5), and a second doped region (10) of a second conductivity type formed inside said first doped region (7); the package (2) comprises a plurality of pins (P1-P10) for the external electrical and mechanical connection; said plurality of elementary functional units (6) is composed of sub-pluralities of elementary functional units (6), the second doped regions (10) of all the elementary functional units (6) of each sub-plurality being contacted by a same respective metal plate (100) electrically insulated from the metal plates (100) contacting the second doped regions (10) of all the elementary functional units (6) of the other sub-pluralities; each of said metal plate (100) is connected, through a respective bonding wire (W1-W5), to a respective pin (P1-P5) of the package (2).

公开(公告)号：DE69228117D1

公开(公告)日：1999-02-18

申请号：DE69228117

申请日：1992-09-23

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAPISARDA CIRINO

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

Abstract: A method for eliminating the bird's beak from selective oxidations of semiconductor electronic devices having a semiconductor substrate (1) which is covered by an oxide layer (2) covered, in turn, by a first layer (3) of nitride, and wherein at least one pit (7,11) is defined for growing an isolation region, comprises the sequential steps of, selectively etching the oxide layer (2) within said pit (7) to define peripheral recesses (6,8) between the substrate (1) and the nitride; occluding said recesses (6,8) with nitride; and growing oxide in said pit (7) so as to form said isolation region contrasting the nitride portions (9,10) which occlude said recesses (6,8).

公开(公告)号：DE69226004T2

公开(公告)日：1999-02-11

申请号：DE69226004

申请日：1992-07-17

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZISA MICHELE ,  BELLUSO MASSIMILIANO ,  PAPARO MARIO

IPC: H03K4/58 ,  H03K5/02 ,  H03K17/06 ,  H03F3/217 ,  H03K17/687 ,  H03K19/017

Abstract: In a bootstrap circuit for a power MOS transistor in the high driver configuration, comprising a first capacitor (C1) chargeable to a first voltage function of the supply voltage of the power transistor (T1), there is present a second capacitor (C2) combined with the first capacitor (C1) in such a way as to make available a second voltage higher than the first voltage and the threshold voltage of the power transistor (T1).

公开(公告)号：DE69321966D1

公开(公告)日：1998-12-10

申请号：DE69321966

申请日：1993-12-24

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MANGIAGLI MARCANTONIO

IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

Abstract: An integrated structure pad assembly for lead bonding to a power semiconductor device chip comprises a chip portion having a top surface covered by a metallization layer (10) and which comprises a first sub-portion (1) wherein functionally active elements of the power device are present; said chip portion comprises at least one second sub-portion (11) wherein no functionally active elements of the power device are present, and a top surface of the metallization layer (10) is elevated over said at least one second sub-portion (11) with respect to the first sub-portion (1) to form at least one protrusion which forms a support surface for a lead.

公开(公告)号：DE69320033D1

公开(公告)日：1998-09-03

申请号：DE69320033

申请日：1993-06-10

Applicant: CONS RIC MICROELETTRONICA

Inventor： PALARA SERGIO

IPC: H01L27/06 ,  H01L21/8249 ,  H01L27/07 ,  H01L29/78 ,  H01L29/72

公开(公告)号：DE69128936T2

公开(公告)日：1998-07-16

申请号：DE69128936

申请日：1991-11-25

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  AIELLO NATALE

IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219 ,  H01L21/76

Abstract: The structure comprises at least arms (1, 2) each formed from a first and a second MOS transistor (M3, M1; M4, M2). Its integrated monolithic construction provides for a type N++ substrate (3) forming a positive potential output terminal (K1) which is overlaid by a type N-epitaxial layer (4). For each of the first transistors (M3; M4) this comprises a type P, P+ insulating region (13, 25; 14, 26) containing a type N+ enriched drain region (15; 16), a type N drain region (19; 20) and, in succession, a type P body region (21; 22) and a pair of type N+ source regions (23; 24) forming a negative potential output terminal (A1) respectively. For each of the second transistors (M1, M2) the structure comprises a type N+ enriched drain region (5, 6) containing a type N drain region (31, 32) and in succession a type P body region (9; 10) and a pair of type N+ regions (11; 12) forming corresponding alternating current inputs (A3, A4) respectively.