公开(公告)号：US20150187892A1

公开(公告)日：2015-07-02

申请号：US14416698

申请日：2012-08-03

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Haizhou Yin ,  Keke Zhang

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/76224 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/1083 ,  H01L29/41725 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66878 ,  H01L29/78 ,  H01L29/7846 ,  H01L29/812

Abstract: A method for manufacturing a semiconductor device is disclosed, comprising: forming a contact sacrificial layer on the substrate, etching the contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial pattern covers the source region and the drain region and has a gate trench that exposes the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching off the contact sacrificial pattern that covers the source region and the drain region so as to form a source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of the double-layer contact sacrificial layer, the method for manufacturing a semiconductor device in accordance with the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the area of contact region, thus effectively reducing the parasitic resistance of the device.

Abstract translation: 公开了一种用于制造半导体器件的方法，包括：在所述衬底上形成接触牺牲层，蚀刻所述接触牺牲层以形成接触牺牲图案，其中所述接触牺牲图案覆盖所述源极区域和所述漏极区域并具有栅极 暴露基板的沟槽; 在所述栅极沟槽中形成栅极间隔物和栅极堆叠结构; 部分地或完全地蚀刻覆盖源极区域和漏极区域的接触牺牲图案，以便形成源极/漏极接触沟槽; 以及在源极/漏极接触沟槽中形成源极/漏极接触。 通过双层接触牺牲层，根据本发明的半导体器件的制造方法有效地减小了栅极间隔物和接触区域之间的间隔并增加了接触区域的面积，从而有效地降低了寄生电阻 的设备。

公开(公告)号：US09029225B2

公开(公告)日：2015-05-12

申请号：US13878046

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/28176 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

Abstract translation: 本公开公开了一种用于制造N型MOSFET的方法，包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的部分包括半导体衬底中的源极/漏极区，源/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入第一金属栅极层; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还 通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。

公开(公告)号：US20150054074A1

公开(公告)日：2015-02-26

申请号：US14389095

申请日：2012-10-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/28079 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/823842 ,  H01L27/11568 ,  H01L29/105 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2029/42388

Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

Abstract translation: 提供半导体器件及其制造方法。 在一个实施例中，该方法可以包括：在衬底上形成第一屏蔽层; 以所述第一屏蔽层为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 在所述第二屏蔽层的侧壁上形成屏蔽间隔物; 用第二屏蔽层和屏蔽间隔物作为掩模形成源极和漏极区域中的另一个; 去除所述屏蔽间隔物的至少一部分; 以及形成栅极电介质层，并且在所述第二屏蔽层的侧壁或所述屏蔽间隔物的可能的剩余部分上形成作为间隔物的栅极导体。

公开(公告)号：US20150041925A1

公开(公告)日：2015-02-12

申请号：US14385101

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/266

CPC classification number: H01L21/28008 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28088 ,  H01L21/28167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.

Abstract translation: 提供P型MOSFET及其制造方法。 该方法可以包括在半导体衬底中形成源极/漏极区域; 在所述半导体衬底上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在所述高K栅极电介质层上形成第一金属栅极层; 通过共形掺杂将掺杂剂注入第一金属栅极层; 并执行退火以改变包括第一金属栅极层，高K栅极电介质和界面氧化物层的栅极堆叠的有效功函数。

公开(公告)号：US20140177039A1

公开(公告)日：2014-06-26

申请号：US14144222

申请日：2013-12-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hailiang Li ,  Changqing Xie ,  Ming Liu ,  Dongmei Li ,  Lina Shi ,  Xiaoli Zhu

IPC: G02B5/18

CPC classification number: G02B5/1871 ,  G02B5/1809 ,  G02B5/1838 ,  G02B5/1857 ,  G02B2005/1804 ,  G03F7/0757 ,  G03F7/2059 ,  G03F7/40

Abstract: A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition. Lastly, removing the gold material on the chrome material outside the ring pattern as well as on and between the grating line patterns, thereby only retaining the gold material on sidewalls of the grating line patterns.

Abstract translation: 公开了一种制造亚波长极紫外金属透射光栅的方法。 在一个方面，该方法包括在硅衬底的背表面上形成氮化硅自支撑膜窗，其两面被抛光，然后用电子束在衬底的前表面上旋涂氮化硅膜 抵制HSQ。 然后，在HSQ上执行电子束直接写入曝光，显影和固定以形成围绕光栅线图案的多个光栅线图案和环形图案。 然后通过磁控溅射在基板的前表面上沉积铬材料。 然后，移除环形图案内的铬材料。 然后，通过原子层沉积在基板的前表面上生长金材料。 最后，除去环形图案之外的铬材料上的金材料以及光栅线图案之间和之间的金材料，从而仅将金材料保留在光栅线图案的侧壁上。

公开(公告)号：US20140011330A1

公开(公告)日：2014-01-09

申请号：US14029157

申请日：2013-09-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/66795 ,  H01L29/785

Abstract: The present application discloses a method for manufacturing a semiconductor device. The method may comprise providing a fin in a semiconductor layer of a SOI substrate, and providing a stack of gate dielectric and gate conductor on only a first side of the fin. The gate conductor may extend laterally away from the first side of the fm in a gate extending direction. The method may comprise doping the fin at its other two opposing sides so as to provide a source region and a drain region. Each of the source and drain regions may have a portion extending laterally away from a second side, opposite to the first side, of the fin in a source/drain extending direction. The gate extending direction and the source/drain extending direction can be parallel to the main surface of the SOI substrate, while being opposite to each other. The method may comprise providing a channel region at a central portion of the fin.

Abstract translation: 本申请公开了一种用于制造半导体器件的方法。 该方法可以包括在SOI衬底的半导体层中提供鳍片，并且仅在鳍片的第一侧上提供栅极电介质层和栅极导体堆叠。 栅极导体可以沿栅极延伸方向横向远离fm的第一侧延伸。 该方法可以包括在其另外两个相对侧掺杂鳍片，以便提供源极区域和漏极区域。 源极和漏极区域中的每一个可以具有在源极/漏极延伸方向上从翅片的与第一侧相对的第二侧向横向延伸的部分。 栅极延伸方向和源极/漏极延伸方向可以平行于SOI衬底的主表面，同时彼此相对。 该方法可以包括在翅片的中心部分处设置通道区域。

公开(公告)号：US20030219683A1

公开(公告)日：2003-11-27

申请号：US10154280

申请日：2002-05-23

Applicant: Institute of Microelectronics.

Inventor： Ranganathan Nagarajan ,  Shajan Mathew ,  Lakshmi Kanta Bera

IPC: G03F007/16 ,  G03F007/20 ,  G03F007/40 ,  G03F007/36 ,  G21K005/00

CPC classification number: G03F7/40 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (

Abstract translation: 描述了在半导体器件和MEMS器件的集成电路的制造期间修整光致抗蚀剂图案的过程。 使用低温（<20℃），高密度氧和氩等离子体和强烈的紫外线辐射的组合来同时修整和硬化ICP腔中的光致抗蚀剂线宽。 作为替代，在ICP等离子体蚀刻之前，可以在泛光曝光工具中执行UV硬化步骤。 另一个选择是首先进行氩等离子体处理以使抗蚀剂硬化，然后在第二步骤中施加氧等离子体来修整光致抗蚀剂。 以可控的方式降低垂直和水平蚀刻速率，这对于在小于100nm的MOS晶体管中产生栅极长度是有用的。 该方法还可以用于可控地增加光致抗蚀剂特征中的空间宽度。

公开(公告)号：US20030218227A1

公开(公告)日：2003-11-27

申请号：US10154279

申请日：2002-05-23

Applicant: Institute of Microelectronics.

Inventor： Janak Singh ,  Uppili Sridhar ,  Ranganathan Nagarajan ,  Quanbo Zou

IPC: H01L031/0232

CPC classification number: B81C1/00142 ,  B81B2201/042 ,  G02B26/0841

Abstract: Design of a micro-mirror switching device and its fabrication in single crystal silicon are described. The device is composed of three main elements: silicon mirror plate with metal-mirror, secondary actuator, and hinge/spring mechanism to integrate the mirror plate with the actuator. p-n junction is first formed on p-type silicon. Trenches are then etched in n-silicon to define the device element boundaries and filled with silicon dioxide. Three layers of sacrificial oxide and two structural poly-silicon layers are deposited and patterned to form device elements. Novel release processes, consisting of backside electrochemical etching in potassium-hydroxide, reactive ion etching to expose oxide-filled trenches from the bottom, and hydrofluoric acid etching of sacrificial oxide layers and oxide in silicon trenches, form the silicon blocks; those that are not attached to structural poly-silicon are sacrificed and those that are attached are left in place to hold together the switching device elements.

Abstract translation: 描述了微镜开关器件的设计及其在单晶硅中的制造。 该装置由三个主要元件组成：具有金属镜的硅镜板，二次致动器和用于将镜板与致动器集成的铰链/弹簧机构。 p-n结首先在p型硅上形成。 然后在n硅中蚀刻沟槽以限定器件元件边界并填充二氧化硅。 沉积和图案化三层牺牲氧化物和两个结构多晶硅层以形成器件元件。 由氢氧化钾中的背面电化学蚀刻，从底部暴露氧化物填充的沟槽的反应离子蚀刻和硅沟槽中的牺牲氧化物层和氧化物的氢氟酸蚀刻组成的新型释放过程形成硅块; 牺牲未附着于结构多晶硅的那些，并且将附着的那些留在适当位置以将开关元件元件保持在一起。

公开(公告)号：US20030008286A1

公开(公告)日：2003-01-09

申请号：US09898124

申请日：2001-07-05

Applicant: Institute of Microelectronics

Inventor： Quanbo Zou ,  Uppili Sridhar

IPC: C12P019/34 ,  C12M001/22 ,  C12M001/00 ,  C12Q001/68 ,  C12M001/34

CPC classification number: B01L3/50851 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00804 ,  B01J2219/00819 ,  B01J2219/00873 ,  B01J2219/00961 ,  B01L7/52 ,  B01L7/54 ,  B01L9/523 ,  B01L2300/0819 ,  B01L2300/1805 ,  F28F13/00

Abstract: It is often desirable to be able to perform an array of micro-chemical reactions simultaneously but with each reaction proceeding at a different temperature and/or for a different time. A classic example is the polymerase chain reaction associated with DNA analysis. In the present invention, this is achieved by means of an apparatus made up of a chip of plastic, or similar low cost material, containing an array of reaction chambers. After all chambers have been filled with reagents, the chip is pressed up against a substrate, typically a printed circuit board, there being a set of temperature balancing blocks between the chip and the substrate. Individually controlled heaters and sensors located between the blocks and the substrate allow each chamber to follow its own individual thermal protocol while being well thermally isolated from all other chambers and the substrate. The latter rests on a large heat sink to avoid temperature drift over time. A process for manufacturing the apparatus is also disclosed.

Abstract translation: 通常期望能够同时执行微量化学反应的阵列，但是每个反应在不同的温度和/或不同的时间进行。 典型的例子是与DNA分析相关的聚合酶链反应。 在本发明中，这通过由包含反应室阵列的塑料芯片或类似的低成本材料构成的装置来实现。 在所有的室已经充满试剂之后，芯片被压靠在基板（通常是印刷电路板）上，在芯片和基板之间存在一组温度平衡块。 位于块体和衬底之间的单独控制的加热器和传感器允许每个腔室遵循其各自的热协议，同时与所有其它腔室和衬底良好地热隔离。 后者放在大型散热器上，以避免温度随时间漂移。 还公开了一种制造该装置的方法。

公开(公告)号：US20020197774A1

公开(公告)日：2002-12-26

申请号：US10186528

申请日：2002-07-01

Applicant: INSTITUTE OF MICROELECTRONICS

Inventor： Shuming Xu ,  Hanhua Feng ,  Pang-Dow Foo

IPC: H01L021/82

CPC classification number: H01L29/66659 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/7835 ,  Y10S438/923

Abstract: In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Abstract translation: 在现有技术中，能够处理高功率的LDMOSFET器件已经通过将源极接触定位在器件的底表面上，通过连接到源极区域通过沉降片而实现良好的散热。 然而，该结构具有差的高频特性。 同样在现有技术中，通过在源极/漏极区域（SOI）之下引入电介质层已经实现了良好的高频性能，但是该结构具有差的功率处理能力。 本发明在同一设备中实现了良好的高频行为以及良好的功率能力。 代替在器件的整个横截面上插入电介质层，电介质层被限制在漏极的重掺杂部分之下，在轻掺杂部分中具有少量的重叠。 详细描述该结构及其制造方法。