公开(公告)号：EP1603239B8

公开(公告)日：2012-11-28

申请号：EP05011771.2

申请日：2005-06-01

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Nitin

IPC: H03K19/003

CPC classification number: H03K19/00315

公开(公告)号：EP1443645B1

公开(公告)日：2010-01-06

申请号：EP03104135.3

申请日：2003-11-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： SAHA, Kaushik ,  MAITI, Srijib Narayan

IPC: H03H17/06

CPC classification number: H03H17/0223 ,  H03H17/06 ,  H03H2017/0298

公开(公告)号：EP1679797B1

公开(公告)日：2009-09-09

申请号：EP05028707.7

申请日：2005-12-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Ranjeet ,  Garg, Paras

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K17/162 ,  H03K19/00361

公开(公告)号：EP1653618A3

公开(公告)日：2008-05-28

申请号：EP05110094.9

申请日：2005-10-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Agarwal, Nitin

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A PWM generator system providing improved duty cycle resolution comprising a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of said PWM waveform, and an additional sub-cycle estimator for determining the additional fractional sub-cycle required to provide said on and off time. A timer is coupled to said integral sub cycle estimator and said additional sub cycle estimator for controlling PWM output switching for the on and off time of the integral and additional fractional sub cycles.

公开(公告)号：EP1806751A1

公开(公告)日：2007-07-11

申请号：EP06127150.8

申请日：2006-12-22

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kohli, Nishu ,  Bhargava, Mudit ,  Kumar, Shishir

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/08

CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized, the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.

Abstract translation: 公开了一种用于引入自定时存储器中的延迟的新方法。 在所提出的方法中，通过在要延迟的信号的路径上引入电容来引入延迟。 电容通过在电路中使用空闲的躺着金属层来实现。 要延迟的信号通过可编程开关连接到这些空闲的电平。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于在所提出的方法中，利用空闲的金属电容，所以可以使用最小量的附加硬件来实现该电路。 由所提出的电路提供的延迟也是存储单元香料特性和核心寄生电容的函数。

公开(公告)号：EP1806640A2

公开(公告)日：2007-07-11

申请号：EP06126405.7

申请日：2006-12-18

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Mandal, Sajal Kumar

IPC: G05F1/565

CPC classification number: G05F1/575

Abstract: The present invention provides a low dropout (LDO) regulator with a stability compensation circuit. A "zero frequency" tracking as well as "non-dominant parasitic poles' frequency reshaping" are performed to achieve a good phase margin for the LDO by means of the compensation circuit. In this compensation method neither a large load capacitor nor its equivalent series resistance (ESR) is needed to stabilize a regulator. LDO regulators, in system on chip (SoC) application, having load capacitors in the range of few nano-Farads to few hundreds of nano-Farads can be efficiently compensated with this compensation method. A dominant pole for the regulator is realized at an internal node and the second pole at an output node of the regulator is tracked with a variable capacitor generated zero over a range of load current to cancel the effect of each other. A third pole of the system is pushed out above the unity gain frequency of the open loop transfer function with the help of the frequency compensation circuit. The compensation technique is very effective in realizing a low power, low-load-capacitor LDO desirable for system on chip applications.

Abstract translation: 本发明提供一种具有稳定补偿电路的低压差（LDO）调节器。 执行“零频”跟踪以及“非显性寄生极”频率整形“，以通过补偿电路为LDO实现良好的相位裕度。 在这种补偿方法中，不需要大的负载电容器及其等效串联电阻（ESR）来稳定稳压器。 LDO调节器在片上系统（SoC）应用中，可以通过这种补偿方法有效地补偿在几纳米法拉范围内的负载电容到几百纳米法拉。 在内部节点实现调节器的主极，并且在负载电流范围内用可变电容器产生零点来跟踪调节器的输出节点处的第二极，以消除彼此的影响。 在频率补偿电路的帮助下，系统的第三极被推出高于开环传递函数的单位增益频率。 补偿技术对于实现片上系统应用所需的低功耗，低负载电容LDO非常有效。

公开(公告)号：EP1750282A1

公开(公告)日：2007-02-07

申请号：EP06118000.6

申请日：2006-07-27

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Dubey, Prashant

IPC: G11C29/00

CPC classification number: G11C29/808 ,  G11C29/846

Abstract: The instant invention provides memory system incorporating shared redundant memories and shared redundant memory architecture. More particularly, the instant invention discloses a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories forming a single logical memory or various memories in close proximity on a SoC. The shared redundancy is achieved by adding a comparator to the redundant element for comparing between the faulty address and the system address and performing a memory operation based on the comparator output. As the redundant memory operations are performed in parallel to the memory structures, it results in reduced setup and hold time. Shared redundancy also results in reduced SoC area.

Abstract translation: 本发明提供的存储器系统包含共享存储器和共享冗余冗余存储器架构。 更具体地，本发明盘松经修饰的存储器用作存储器系统之间的共享冗余存储器。 这些存储器系统可具有几个较小的记忆形成在靠近上的SoC的一个单一的逻辑存储器或各种存储器。 共享冗余是通过将比较器的冗余元件的故障地址和所述系统地址之间进行比较并执行存储器操作基于所述比较器的输出来实现的。 为冗余存储器操作是并行进行的到所述存储器的结构，它导致降低的建立和保持时间。 所以共享降低SoC的面积冗余结果。

公开(公告)号：EP1675266A2

公开(公告)日：2006-06-28

申请号：EP05107860.8

申请日：2005-08-26

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chatterjee, Kallol ,  Jain, Deependra

IPC: H03K23/66 ,  H03K23/58

CPC classification number: H03K23/665 ,  H03K21/40 ,  H03K23/667

Abstract: A programmable high-speed frequency divider, in which stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified to reduce the area and circuit complexity. A start-up circuitry has been introduced within the said frequency-divider to ensure that the frequency-divider will never go into false state.

Abstract translation: 一种可编程高速分频器，其中能够以可编程分频比编程的用于形成分频器的级被简化以减小面积和电路复杂度。 在所述分频器内引入了启动电路，以确保分频器永远不会进入假状态。

公开(公告)号：EP1432126A3

公开(公告)日：2006-06-14

申请号：EP03104727.7

申请日：2003-12-16

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： BAL, Ankur ,  KHANNA, Namerita

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A high performance interconnect architecture is described that provides reduced delay minimized electromigration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

公开(公告)号：EP1653747A2

公开(公告)日：2006-05-03

申请号：EP05022773.5

申请日：2005-10-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kaushik, Saha ,  Chakraborty, Chiranjib ,  Chatterjee, Subrata

IPC: H04N7/62

CPC classification number: H04N21/4305

Abstract: A system for clock recovery in digital video communication comprising a delay measurement block for generating PCR input signals and for continuously determining time interval between successive PCR input signals, a first storage device for generating a first PCR signal corresponding to said time interval between arrival of successive PCR input signals, a PCR inter-arrival time computation filtering device for determining the average time of arrival difference between successive PCR packets. An error correction device for minimizing the error in the average PCR difference between successive PCR packets, a controlled system clock generator connected to the output of said error correction device to generate system clock, a second storage device for generating a first system clock output, a controlled clock period difference computation element for computing the clock period difference between said first and second system clock output, and said controlled clock period difference computation element is coupled at its output to said error correction device to form a feedback circuit for minimizing the error between said system clock output and successive PCR differences observed.

Abstract translation: 一种用于数字视频通信中的时钟恢复的系统，包括用于产生PCR输入信号的延迟测量块和用于连续地确定连续的PCR输入信号之间的时间间隔的第一存储装置，用于产生对应于连续到达之间的所述时间间隔的第一PCR信号 PCR输入信号，PCR到达间时间计算滤波装置，用于确定连续PCR分组之间的平均到达时差。 一种用于最小化连续PCR分组之间的平均PCR差异误差的纠错装置，连接到所述纠错装置的输出以产生系统时钟的受控系统时钟发生器，用于产生第一系统时钟输出的第二存储装置， 控制时钟周期差计算元件，用于计算所述第一和第二系统时钟输出之间的时钟周期差，并且所述受控时钟周期差计算元件在其输出处耦合到所述纠错装置，以形成反馈电路，以使所述第一和第二系统时钟输出之间的误差最小化 观察系统时钟输出和连续的PCR差异。