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    CMOS AND PRESSURE SENSOR INTEGRATED ON A CHIP AND FABRICATION METHOD
    141.
    发明公开
    CMOS AND PRESSURE SENSOR INTEGRATED ON A CHIP AND FABRICATION METHOD 审中-公开
    集成在芯片上的CMOS和压力传感器及其制造方法

    公开(公告)号：EP3299787A1

    公开(公告)日：2018-03-28

    申请号：EP17181988.1

    申请日：2017-07-18

    Applicant: NXP USA, Inc.

    Inventor： LIU, Lianjun ,  BOSE, Amitava

    IPC: G01L9/00 ,  B81C1/00

    CPC classification number: B81B3/0027 ,  B81B2201/0264 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/0132 ,  B81C2201/053 ,  B81C2203/0714 ,  B81C2203/075 ,  G01L9/0042 ,  G01L9/0045 ,  G01L9/0052 ,  G01L9/0054

    Abstract: A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.

    Abstract translation: 一种器件包括具有第一和第二硅层的绝缘体上硅（SOI）衬底，绝缘体层插入它们之间。 具有第一导电类型的结构层形成在第一硅层上。 具有与第一导电类型相反的第二导电类型的阱区域形成在结构层中，并且电阻器在阱区域中扩散。 在阱区和电阻器上形成金属化结构。 第一腔体延伸穿过覆盖阱区域的金属化结构，并且第二腔体延伸穿过第二硅层，第二腔体在第一硅层和绝缘体层中的一个处停止。 介于第一腔和第二腔之间的井区域限定压力传感器的隔膜。 可以使用CMOS制造工艺在SOI衬底上同时制造集成电路和压力传感器。

    Method of making a MEMS device
    142.
    发明公开
    Method of making a MEMS device 审中-公开
    一种用于制造微机电系统器件的工艺

    公开(公告)号：EP2476644A3

    公开(公告)日：2014-01-22

    申请号：EP11184861.0

    申请日：2011-10-12

    Applicant: Freescale Semiconductor, Inc.

    Inventor： Karlin, Lisa H ,  Kierst, David W. ,  Liu, Lianjun ,  Liu, Wie ,  Montez, Ruben B. ,  Steimle, Robert F.

    IPC: B81C1/00

    CPC classification number: B81C1/00801 ,  B81B2207/07 ,  B81C2201/053

    Abstract: A method of forming a MEMS device (10) includes forming a sacrificial layer (34) over a substrate (12). The method further includes forming a metal layer (42) over the sacrificial layer (34) and forming a protection layer (44) overlying the metal layer (42). The method further includes etching the protection layer (44) and the metal layer (42) to form a structure (56) having a remaining portion of the protection layer formed over a remaining portion of the metal layer. The method further includes etching the sacrificial layer (34) to form a movable portion of the MEMS device, wherein the remaining portion of the protection layer protects the remaining portion of the metal layer during the etching of the sacrificial layer (34) to form the movable portion of the MEMS device (10).

    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER
    143.
    发明公开
    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER 审中-公开
    VERFAHRENFÜRMINIMIERTE SPANBILDUNG贝德TRENNUNG VON MEMS芯片AUF EINEM WAFER

    公开(公告)号：EP2567401A4

    公开(公告)日：2013-12-25

    申请号：EP11778212

    申请日：2011-05-03

    Applicant: S3C INC

    Inventor： HORTON ROGER ,  HUSSAIN JAVED

    IPC: B81C1/00 ,  H01L23/58

    CPC classification number: B81B7/0058 ,  B81C1/00888 ,  B81C2201/053 ,  G01L9/0055 ,  H01L21/78

    Abstract: A method for separating a plurality of dies on a Micro-Electro-Mechanical System (MEMS) wafer comprising scribing a notch on a first side of the wafer between at least two of the plurality of dies on a first surface and depositing a metal on the first surface of the plurality of dies. The method further comprises scribing a second side of the wafer between at least two of the plurality of dies from a second surface thereof through the notch. The first side and second side are substantially parallel and opposite each other and the first surface and the second surface are substantially parallel and opposite each other. In a process in accordance with the present invention, a method to minimize chipping of the bonding portion of a MEMs device during sawing of the wafer is provided, which minimally affects the process steps associated with separating the die on a wafer.

    Abstract translation: 一种用于在微电子机械系统（MEMS）晶片上分离多个裸片的方法，包括在第一表面上的多个裸片中的至少两个裸片之间在晶片的第一侧上划刻凹口，并且在第一表面上沉积金属 多个管芯的第一表面。 所述方法进一步包括在所述多个管芯中的至少两个之间从其第二表面通过所述凹口划刻所述晶片的第二侧。 第一侧面和第二侧面基本平行并且彼此相对，并且第一表面和第二表面基本平行且彼此相对。 在根据本发明的工艺中，提供了一种在锯切晶片期间最小化MEMS器件的键合部分的碎裂的方法，其最小程度地影响与将晶粒分离在晶片上相关的工艺步骤。

    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER
    144.
    发明公开
    PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER 审中-公开
    PROCEDURE FOR MINIMIZED SPAN教育在MEMS芯片上的晶片中的分离

    公开(公告)号：EP2567401A1

    公开(公告)日：2013-03-13

    申请号：EP11778212.8

    申请日：2011-05-03

    Applicant: S3C, Inc.

    Inventor： HORTON, Roger ,  HUSSAIN, Javed

    IPC: H01L23/58

    CPC classification number: B81B7/0058 ,  B81C1/00888 ,  B81C2201/053 ,  G01L9/0055 ,  H01L21/78

    Abstract: A method for separating a plurality of dies on a Micro-Electro-Mechanical System (MEMS) wafer comprising scribing a notch on a first side of the wafer between at least two of the plurality of dies on a first surface and depositing a metal on the first surface of the plurality of dies. The method further comprises scribing a second side of the wafer between at least two of the plurality of dies from a second surface thereof through the notch. The first side and second side are substantially parallel and opposite each other and the first surface and the second surface are substantially parallel and opposite each other. In a process in accordance with the present invention, a method to minimize chipping of the bonding portion of a MEMs device during sawing of the wafer is provided, which minimally affects the process steps associated with separating the die on a wafer.

    Surfactant-enhanced protection of micromechanical components from galvanic degradation
    149.
    发明公开
    Surfactant-enhanced protection of micromechanical components from galvanic degradation 审中-公开
    通过使用表面活性剂从电分解改进的保护微机械元件

    公开(公告)号：EP1403211A2

    公开(公告)日：2004-03-31

    申请号：EP03255693.8

    申请日：2003-09-11

    Applicant: PTS Corporation

    Inventor： Staple, Bevan ,  Buriak, Jilian

    IPC: B81B3/00

    CPC classification number: B82Y30/00 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0114 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/053

    Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate (step 102). The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component (step 104 or 106). The sacrificial material is removed with a release solution (step 108 or 110). At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.

    Abstract translation: 形成微机电结构涉及沉积牺牲和结构材料在底物，至少覆盖所述结构层的一部分与保护性材料，其中所述保护性材料构成的电势小于或等于所述组件的电势，并 用剥离溶液除去牺牲材料。 形成微机电结构涉及沉积牺牲和结构材料在基材以形成与基材，其中，所述结构层构成的电势比所述部件的电势更高的电连接的部件上的结构层; 至少覆盖有保护性材料，其中所述保护性材料构成的电势小于或等于所述组件的电势，所述结构层的一部分; 并用剥离溶液，其中该释放溶液和保护材料中的至少一个被surfactanated除去牺牲材料。 因此独立claimsoft被包括为用于制造装置，其包括沉积材料在基板的层的方法，至少覆盖材料层的一部分与保护材料，浸渍基材电解质在一个，以及将 电解质和基板之间的电势差。

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