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公开(公告)号：JP2000346934A
公开(公告)日：2000-12-15
申请号：JP2000106524
申请日：2000-04-07
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART LUC
Abstract: PROBLEM TO BE SOLVED: To measure distance to a terminal on a transponder side by comparing DC voltage level information when an oscillation circuit being arranged on the upstream side from the DC voltage rectification means of a transponder is tuned or detuned from a fixed frequency. SOLUTION: The transponder 30 is provided with an inductance L2 and a capacitor C2 between terminals 11 and 12 as an oscillation circuit. The voltage of a capacitor Ca is subjected to single half-wave rectification by a diode D. A reference voltage 15 corresponds to the negative terminal of the capacitor Ca that is connected to the terminal 12. A DC supply voltage Va is inputted to input DET being connected to the microprocessor of an electronic block 31. A capacitor C3 is connected in series with a switch K1 and is located between the terminals 11 and 12. When the transponder 30 is in a terminal region, power is supplied, the transistor K1 is turned on, and an oscillation circuit is turned for recharging the terminal DET. After that, the transistor K1 is turned off, and the circuit is detuned and the terminal DET is recharged again. The two DC voltage values are compared and are stored at a single bit.
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公开(公告)号：JP2000330787A
公开(公告)日：2000-11-30
申请号：JP2000135045
申请日：2000-05-08
Applicant: ST MICROELECTRONICS SA
Inventor： WOJCIESZAK LAURENT , COFLER ANDREW
Abstract: PROBLEM TO BE SOLVED: To prevent electric power and a load from being applied on a memory access bus by locking a prefetch buffer for further access to a program memory when all loop instructions are present in the prefetch buffer. SOLUTION: A matching part 20 inspects a loop start address by a compactor 77 as to the address of a matching program counter 36. When the same loop start address match is stored in a special buffer 75, this means that a loop is completely included in the prefetch buffer 22. In this case, a lock signal is sent to the prefetch buffer 22. All loop instructions are held in the prefetch buffer 22 with a frequency where the loop instructions need to be executed. Therefore, the lock signal eliminates the need to take the loop instructions out of a program memory repeatedly until the loop is repeated with the prescribed frequency.
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公开(公告)号：JP2000228637A
公开(公告)日：2000-08-15
申请号：JP36095499
申请日：1999-12-20
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART LUC , BARDOUILLET MICHEL
Abstract: PROBLEM TO BE SOLVED: To avoid a transmission gap (distance where a terminal can detect a transponder) and also to maintain a maximum system range by providing two capacitive modulating means and connecting the reference terminal of each modulating means to the reference supply potential of an electronic circuit on the secondary side of a rectifying means. SOLUTION: This transponder 10' is formed from an oscillation circuit consisting of an inductance L2 and a capacitor C2 parallelly connected between two alternating current input terminals 11 and 12 of a rectifier bridge 13 consisting of rectifier diodes D1 to D4. The rectifier output terminals 14 and 15 of the bridge 13 supply a service voltage to an electronic circuit 17 such as a processor P through a filtering capacitor Ca. Two capacitive modulating means (consisting of C3, K1, C4 and K2) respectively connected to the terminals 11 and 12 of both ends of a dielectric element L2 of an oscillation circuit are included, and the reference terminal of each modulating means is connected to a reference supply potential 15 of the circuit 17 on the secondary side of a rectifying means 13.
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公开(公告)号：JP2000224238A
公开(公告)日：2000-08-11
申请号：JP2000020024
申请日：2000-01-28
Applicant: ST MICROELECTRONICS SA
Inventor： MONIOT PASCAL , COPPOLA MARCELLO
Abstract: PROBLEM TO BE SOLVED: To obtain a system that manages data transmission on a single channel from a plurality of data transmitters. SOLUTION: A data source data transmission system is a system that transmits a request with usual priority when a data source is ready for transmission of a data packet, and includes a round robin circuit 12 that causes packet transmission by a data source being a request presentation object before present analysis time by checking a request in a consecutive analysis time. This system includes a queue having two positions to which a packet is soon written for each data source when the data source is ready, and when the queue includes a single packet, a request with usual priority is presented and the queue includes two packets, the request with higher priority is presented and transmission of the packet of each queue relating to the request with higher priority is caused and when the request with higher priority is not presented before the analysis time, the round robin circuit 12 is used only to cause the transmission of the packet of the queue relating to the request with the usual priority.
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公开(公告)号：JP2000156873A
公开(公告)日：2000-06-06
申请号：JP11707699
申请日：1999-04-23
Applicant: ST MICROELECTRONICS SA
Inventor： LEMAITRE REGIS
Abstract: PROBLEM TO BE SOLVED: To obtain a system having balanced responses of a direct channel and a delay channel by providing a continuous compensation low-pass filter in a 2nd channel to take balance of pulse responses of two channels. SOLUTION: This line is provided with a 1st channel which is provided with at least one continuous low-pass filter 20 performing smoothing and elimination of a clock residual and is sampled and a 2nd channel into which a continuous low-pass compensation filter 21 is inserted to take balance of pulse responses of the two channels and which is not sampled. Thus, the filter 21 is inserted into the direct channel to take balance of the responses of the direct channel and a delay channel. Consequently, it is possible to obtain a system taking balanced responses of the direct channel and the delay channel.
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Patent Agency Ranking
公开(公告)号：JP2000148931A
公开(公告)日：2000-05-30
申请号：JP31042199
申请日：1999-10-29
Applicant: ST MICROELECTRONICS SA
Inventor： GAULTIER JEAN-MARIE
Abstract: PROBLEM TO BE SOLVED: To obtain an identification method that has a form in which a calling unit transmits at least two different types of markers, i.e., a 1st type of a marker deciding the start of a time slot in a sequence and a 2nd type of a marker making a card be in a prescribed state after a calling message and they are received and interpreted by the card. SOLUTION: This improvement is about a process for identifying an electronic card existing in an identification area, a card responds to a calling message (CALL) transmitted by a calling unit by transmitting a response message (R0) determined by a specific time slot (W0) in the sequence of time slots, the calling unit transmits at least two different types of markers (M1 and M2) after the calling message (CALL), they are received and interpreted by the card, the 1st type of a marker (M1) decides the start of a time slot in the sequence and the 2nd type of a marker (M2) makes the card be in a prescribed state. It is possible to interrupt the card identification procedures before the sequence is finished by this method.
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公开(公告)号：JP2000133703A
公开(公告)日：2000-05-12
申请号：JP30118299
申请日：1999-10-22
Applicant: ST MICROELECTRONICS SA
Inventor： ANCEAU CHRISTINE
IPC: H01L21/20 , H01L21/316 , H01L21/32 , H01L21/762
Abstract: PROBLEM TO BE SOLVED: To prevent the occurrence of irregularities on the interface in a perpendicular section corresponding to a power component by removing an insulating layer and a thin silicon layer, growing an epitaxial layer, flattering the layer, and forming a perpendicular insulating wall on the periphery of a portion in which the thin insulating layer remains. SOLUTION: A single-crystal thin silicon layer 12 and a portion of a lower silicon oxide layer 11 are removed downwardly to the upper surface 14 of a single-crystal silicon 10. Next, an epitaxial growth is performed for silicon, a single-crystal silicon layer 24 with the same crystal orientation as that of the substrate 10 is grown on the visual surface of the substrate, and a single- crystal silicon 25 with the same crystal orientation as that of the thin silicon layer 22 is grown on the layer 22. A section 27 with crystalline irregularities exists on the boundary between the layer 24 and the layer 25. After performing planarization through a chemical-mechanical polishing, a perpendicular insulating wall 29 is formed. As a result, the boundary with irregularities will not exist in the perpendicular section which corresponds to a power component.
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公开(公告)号：JP2000124472A
公开(公告)日：2000-04-28
申请号：JP29533399
申请日：1999-10-18
Applicant: ST MICROELECTRONICS SA
Inventor： MATHIEU ROY
IPC: H01L29/06 , H01L29/40 , H01L29/861
Abstract: PROBLEM TO BE SOLVED: To restrain a trouble generated by breakdown voltage of a power constituent part when a mutual connection track exists. SOLUTION: The power constituent part is formed in an N-type silicon board defined by a P-type wall surface and has a lower surface including a first P-type region 3 connected to the wall surface, an upper surface including a second P-type region and a conductive layer extending between the second region 4, and a wall surface on a board. The constituent part includes a third N-type region 22 of high doping level formed under a layer part which is almost in a middle between an outer circumferential edge part of the second region 4 and an inner circumferential edge part of a wall surface in a substrate 1. The third region 22 is in contact with a filed plate 21 which extends in both sides of the third region 22 in the direction of a wall surface and the direction of the third region 22.
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公开(公告)号：JP2000049295A
公开(公告)日：2000-02-18
申请号：JP19889599
申请日：1999-07-13
Applicant: ST MICROELECTRONICS SA , KONINKL PHILIPS ELECTRONICS NV
Inventor： GRIS YVON , TROILLARD GERMAINE , MOURIER JOCELYNE , GUELEN JOS , LUNARDI GENEVIEVE , BANVILLET HENRI , OBERLIN JEAN-CLAUDE , MADDALON CATHERINE
IPC: H01L21/302 , H01L21/02 , H01L21/3065 , H01L21/768 , H01L21/822 , H01L27/04
Abstract: PROBLEM TO BE SOLVED: To provide a method which has compatibility with the existing CMOS components manufacturing process in manufacturing a capacitor, having little possibility of causing the dielectric breakdown. SOLUTION: A first metal layer is deposited and etched with leaving a region 12, corresponding to a capacitor plate and contact region 13 on the first metal layer, an input layer 15 is deposited between metallization layers, a first opening is formed into an upper part of the capacitor plate 12, a thin insulation layer 17 is deposited, a second opening 20 is formed into an upper part of the contact region, a second metal layer 24 is deposited for completely filling the opening 20, a physical-chemical etching is applied to suppress the outside region of the second metal layer, and a third metal layer is deposited to cause to be left at positions 31, 32 on the third metal layer above the contact region and capacitor region.
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公开(公告)号：JP2000029703A
公开(公告)日：2000-01-28
申请号：JP9497599
申请日：1999-04-01
Applicant: ST MICROELECTRONICS SA
Inventor： FUIN DIDIER
Abstract: PROBLEM TO BE SOLVED: To provide a super-scalar processor which has maximum efficiency for the execution of a loop, including a memory access instruction. SOLUTION: A processor includes at least one memory access unit (MENU) 10 which provides a readout or write-in address for the address bus of a memory 16 as a readout or write-in instruction is executed, a computing and logic unit(ALU) 12, which operates in parallel to the memory access unit and is arranged at least to provide data for the data bus of the memory while the memory access unit provides a write address, and a stored address quene (STAQ) in which respective write addresses provided by the memory access unit waiting until the availability of the data is written are stored.
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