SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING

    公开(公告)号:ZA201408076B

    公开(公告)日:2019-05-29

    申请号:ZA201408076

    申请日:2014-11-04

    Applicant: IBM

    Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.

    TEMPORARILY SUPPRESSING PROCESSING OF A RESTRAINED STORAGE OPERAND REQUEST

    公开(公告)号:CA3037265A1

    公开(公告)日:2018-07-19

    申请号:CA3037265

    申请日:2018-01-09

    Applicant: IBM

    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

    Dynamic enablement of multithreading

    公开(公告)号:AU2015238632B2

    公开(公告)日:2018-04-26

    申请号:AU2015238632

    申请日:2015-03-19

    Applicant: IBM

    Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

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