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    Dopant selective reactive ion etching of silicon carbide
    162.
    发明授权
    Dopant selective reactive ion etching of silicon carbide 有权
    掺杂剂选择性反应离子蚀刻碳化硅

    公开(公告)号：US09452926B1

    公开(公告)日：2016-09-27

    申请号：US13561359

    申请日：2012-07-30

    Applicant: Robert Okojie

    Inventor： Robert Okojie

    IPC: B81C1/00

    CPC classification number: B81C1/00531 ,  B81B2201/0264 ,  B81B2203/0109 ,  B81C1/0015 ,  B81C1/00555 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0136

    Abstract: A method for selectively etching a substrate is provided. In one embodiment, an epilayer is grown on top of the substrate. A resistive element may be defined and etched into the epilayer. On the other side of the substrate, the substrate is selectively etched up to the resistive element, leaving a suspended resistive element.

    Abstract translation: 提供了一种用于选择性蚀刻衬底的方法。 在一个实施例中，在衬底的顶部上生长外延层。 可以限定电阻元件并蚀刻到外延层中。 在衬底的另一侧，衬底被选择性蚀刻到电阻元件上，留下一个悬置的电阻元件。

    Method for producing micromechanical patterns having a relief-like sidewall outline shape or an adjustable angle of inclination
    165.
    发明授权
    Method for producing micromechanical patterns having a relief-like sidewall outline shape or an adjustable angle of inclination 失效
    用于制造具有浮雕状侧壁轮廓形状或可调节倾斜角度的微机械图案的方法

    公开(公告)号：US08501516B2

    公开(公告)日：2013-08-06

    申请号：US12740607

    申请日：2008-10-13

    Applicant: Franz Laermer ,  Tino Fuchs ,  Christina Leinenbach

    Inventor： Franz Laermer ,  Tino Fuchs ,  Christina Leinenbach

    IPC: H01L21/306

    CPC classification number: B81C1/00103 ,  B81B2203/0384 ,  B81C2201/0136

    Abstract: A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon semiconductor substrate, by dry chemical etching of the SiGe mixed semiconductor layer; the sidewall outline shape of the micromechanical pattern being developed by varying the germanium proportion in the SiGe mixed semiconductor layer that is to be etched; a greater germanium proportion being present in regions that are to be etched more strongly; the variation in the germanium proportion in the SiGe mixed semiconductor layer being set by a method selected from the group including depositing a SiGe mixed semiconductor layer having varying germanium content, introducing germanium into a silicon semiconductor layer or a SiGe mixed semiconductor layer, introducing silicon into a germanium layer or an SiGe mixed semiconductor layer and/or by thermal oxidation of a SiGe mixed semiconductor layer.

    Abstract translation: 一种用于生产具有凸起状侧壁轮廓形状或能够被设定的倾斜角的微机械图案的方法，从存在于或沉积在硅半导体衬底上的SiGe混合半导体层中蚀刻微机械图案， 通过干法化学蚀刻SiGe混合半导体层; 通过改变要蚀刻的SiGe混合半导体层中的锗比例来显影微机械图案的侧壁轮廓形状; 存在于要被更强蚀刻的区域中更大的锗比例; SiGe混合半导体层中的锗比例的变化通过选自包括沉积具有不同锗含量的SiGe混合半导体层，将锗引入到硅半导体层或SiGe混合半导体层中的方法来设置，将硅引入 锗层或SiGe混合半导体层和/或通过SiGe混合半导体层的热氧化。

    Single Crystal Silicon Membrane with a Suspension Layer, Method for Fabricating the Same, and a Micro-Heater
    166.
    发明申请
    Single Crystal Silicon Membrane with a Suspension Layer, Method for Fabricating the Same, and a Micro-Heater 有权
    具有悬浮层的单晶硅膜，其制造方法和微加热器

    公开(公告)号：US20130062738A1

    公开(公告)日：2013-03-14

    申请号：US13482020

    申请日：2012-05-29

    Applicant: Chung-Nan Chen

    Inventor： Chung-Nan Chen

    IPC: H01L29/04 ,  H01L21/306

    CPC classification number: B81C1/00158 ,  B81C1/00595 ,  B81C2201/0136 ,  H05B3/141

    Abstract: To form a single crystal silicon membrane with a suspension layer, a single crystal silicon substrate with crystal orientation is prepared. A doped layer is formed on the top surface of the single crystal silicon substrate. Multiple main etching windows are formed through the doped layer. A cavity is formed through the single crystal silicon substrate by anisotropic etching. The doped layer is above the cavity to form a suspension layer. If two electrode layers are formed on the two ends of the suspension layer, a micro-heater is constructed. The main etching windows extend in parallel to a crystal plane {111}. By both the single crystal structure and different impurity concentrations of the single crystal silicon substrate, the single crystal silicon substrate has a higher etch selectivity. When a large-area cavity is formed, the thickness of the suspension layer is still controllable.

    Abstract translation: 为了形成具有悬浮层的单晶硅膜，制备晶体取向<111>的单晶硅衬底。 在单晶硅衬底的顶表面上形成掺杂层。 通过掺杂层形成多个主蚀刻窗口。 通过各向异性蚀刻通过单晶硅衬底形成空穴。 掺杂层在空腔之上以形成悬浮层。 如果在悬浮层的两端形成两个电极层，则构成微加热器。 主蚀刻窗平行于晶面{111}延伸。 通过单晶硅衬底的单晶结构和不同的杂质浓度，单晶硅衬底具有较高的蚀刻选择性。 当形成大面积腔时，悬浮层的厚度仍然可控。

    ETCHING TRENCHES IN A SUBSTRATE
    167.
    发明申请
    ETCHING TRENCHES IN A SUBSTRATE 有权
    蚀刻在基板上的横梁

    公开(公告)号：US20120264307A1

    公开(公告)日：2012-10-18

    申请号：US13088106

    申请日：2011-04-15

    Applicant: Srivatsa G. Kundalgurki ,  James F. McHugh

    Inventor： Srivatsa G. Kundalgurki ,  James F. McHugh

    IPC: H01L21/302

    CPC classification number: H01L21/02057 ,  B81C1/00063 ,  B81C1/00626 ,  B81C2201/0136 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3083

    Abstract: Etch stabilizing ions (37) are introduced, e.g., by ion implantation (34), into a portion (36) of a substrate (20) underlying an etch window (24) in a masking layer (22) covering the substrate (20), where a trench (26) is desired to be formed. When the portion (36) of the substrate (20) containing the etch stabilizing ions (37) is etched to form the trench (26), the etch stabilizing ions (37) are progressively released at the etch interface (28′) as etching proceeds, substantially preventing gas micro-bubbles or other reaction products at the etch interface (28′) from disrupting etching. Using this method (700), products containing trenches (26) are much more easily formed and such trenches (26) have much smoother interior surface (28).

    Abstract translation: 蚀刻稳定离子（37）例如通过离子注入（34）引入覆盖衬底（20）的掩模层（22）中的蚀刻窗（24）下面的衬底（20）的部分（36） ，其中希望形成沟槽（26）。 当蚀刻包含蚀刻稳定离子（37）的衬底（20）的部分（36）以形成沟槽（26）时，蚀刻稳定离子（37）在蚀刻界面（28'）处逐渐释放，如蚀刻 进行，基本上防止蚀刻界面（28'）处的气体微气泡或其他反应产物破坏蚀刻。 使用该方法（700），包含沟槽（26）的产品更容易形成，并且这种沟槽（26）具有更平滑的内表面（28）。

    METHOD FOR CREATING A MICROMECHANICAL MEMBRANE STRUCTURE AND MEMS COMPONENT
    168.
    发明申请
    METHOD FOR CREATING A MICROMECHANICAL MEMBRANE STRUCTURE AND MEMS COMPONENT 有权
    用于创建微机电薄膜结构和MEMS组件的方法

    公开(公告)号：US20120126346A1

    公开(公告)日：2012-05-24

    申请号：US13290905

    申请日：2011-11-07

    Applicant: Arnim Hoechst ,  Jochen Reinmuth ,  Brett Diamond

    Inventor： Arnim Hoechst ,  Jochen Reinmuth ,  Brett Diamond

    IPC: H01L29/84 ,  H01L21/02

    CPC classification number: B81C1/00595 ,  B81B2201/0235 ,  B81B2203/0127 ,  B81B2203/0181 ,  B81B2203/053 ,  B81C2201/0112 ,  B81C2201/0133 ,  B81C2201/0136

    Abstract: In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least the intended membrane surface area. In addition, in a DRIE (deep reactive ion etching) process applied to the back side of the silicon substrate, a cavity is created beneath the doped area, which DRIE process is aborted before the cavity reaches the doped area. The cavity is then deepened in a KOH etching process in which the doped substrate area functions as an etch stop, so that the doped substrate area remains as a basic membrane over the cavity.

    Abstract translation: 在制造微机械膜结构的方法中，在硅衬底的前侧产生掺杂区域，其掺杂区域的深度对应于所需的膜厚度，并且其掺杂区域的横向范围至少覆盖预期的 膜表面积。 另外，在施加到硅衬底的背侧的DRIE（深反应离子蚀刻）工艺中，在掺杂区域之下产生空腔，在空腔到达掺杂区域之前DRIE工艺被中止。 然后在KOH蚀刻工艺中加深空腔，其中掺杂衬底区域用作蚀刻停止层，使得掺杂衬底区域保持为空腔上的基本膜。

    METHOD OF FORMING AN UNDERCUT MICROSTRUCTURE
    169.
    发明申请
    METHOD OF FORMING AN UNDERCUT MICROSTRUCTURE 失效
    形成底层微结构的方法

    公开(公告)号：US20110250397A1

    公开(公告)日：2011-10-13

    申请号：US12842334

    申请日：2010-07-23

    Applicant: Tzyy-Jiann WANG ,  Yueh-Hsun TSOU

    Inventor： Tzyy-Jiann WANG ,  Yueh-Hsun TSOU

    IPC: B32B3/10 ,  C23F1/02

    CPC classification number: B81C1/00103 ,  B81B2203/0384 ,  B81C1/00571 ,  B81C2201/0136 ,  G02B6/12007 ,  G02B6/136 ,  G02B2006/1204 ,  G02B2006/12045 ,  Y10T428/24479

    Abstract: A method of forming an undercut microstructure includes: forming an etch mask on a top surface of a substrate; forming, on a top surface of the etch mask, an ion implantation mask having a top surface that is smaller than the top surface of the etch mask and that does not extend beyond the top surface of the etch mask; ion implanting the substrate in the presence of the etch mask and the ion implantation mask so that a damaged region is generated at a depth below an area of the surface that is not masked by the ion implantation mask; and etching the surface of the substrate until the damaged region is removed.

    Abstract translation: 形成底切微结构的方法包括：在衬底的顶表面上形成蚀刻掩模; 在所述蚀刻掩模的顶表面上形成具有比所述蚀刻掩模的顶表面小的顶表面并且不延伸超过所述蚀刻掩模的顶表面的离子注入掩模; 在蚀刻掩模和离子注入掩模的存在下离子注入衬底，使得在未被离子注入掩模掩蔽的表面的区域下方的深度处产生损伤区域; 并蚀刻衬底的表面直到损坏的区域被去除。

    Method of fabricating a MEMS/NEMS electromechanical component
    170.
    发明授权
    Method of fabricating a MEMS/NEMS electromechanical component 有权
    制造MEMS / NEMS机电元件的方法

    公开(公告)号：US07906439B2

    公开(公告)日：2011-03-15

    申请号：US12488898

    申请日：2009-06-22

    Applicant: François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

    Inventor： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: B81C1/00507 ,  B81B2201/0271 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0177 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072 ,  H03H9/175 ,  H03H9/2436 ,  Y10S438/933

    Abstract: The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second region between said cavity and said interface layer; wherein the first and second portions of the substrate are constituted respectively from first and second substrates that are assembled together by bonding, at least one of them including at least one said interface layer over at least a fraction of its surface.

    Abstract translation: 本发明提供一种在至少一个基板上具有有源元件的制造方法和机电装置，该方法具有以下步骤：a）制造具有第一部分，界面层和第二部分的非均相基底，第一部分 包括夹在形成于第一单晶材料中的第一和第二区域之间的一个或多个掩埋区域，第一区域延伸到第一部分的表面，第二区域延伸到界面层，至少一个所述掩埋区域 至少部分地由第二单晶材料制成，以使其相对于第一和第二区域选择性地具有攻击性; b）从所述第一部分的表面和所述第一区域制造开口，所述第一区域开放到至少一个所述掩埋区域; 以及c）蚀刻至少一个掩埋区域的至少一部分以形成至少一个空腔，以便限定至少一个有源元件，所述至少一个有源元件是所述腔和所述界面层之间的第二区域的至少一部分; 其中所述基板的第一和第二部分分别由通过粘接而组装在一起的第一和第二基板构成，其中至少一个在其表面的至少一部分上包括至少一个所述界面层。

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