公开(公告)号：US20050230829A1

公开(公告)日：2005-10-20

申请号：US11081658

申请日：2005-03-17

Applicant: Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

Inventor： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

IPC: H05K1/02 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09281 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on the package substrate 5. At least one of the lands 8 that make up columns that are located closest to each of the main sides that make up the outer edges of the semiconductor package has an interconnection 9 that extends from the land 8 along the surface of the package substrate. The interconnection 9 is formed such that the part that contacts the land 8 is located closer to a line that passes through the center of the land 8 and that is orthogonal to a line that connects the center of the land 8 with the center of the semiconductor package 2 than to the line that connects the center of the land 8 with the center of the semiconductor package 2.

Abstract translation: 半导体器件设置有半导体封装2和封装衬底5，封装衬底5具有通过焊料凸点4电连接到半导体封装2的焊盘8。 在封装基板5上形成有多个列，其中布置有多个焊盘8。 构成最靠近构成半导体封装的外边缘的每个主侧的列的焊盘8中的至少一个具有从焊盘8沿着封装基板的表面延伸的互连9。 互连9形成为使得接触焊盘8的部分更靠近通过焊盘8的中心的线并且与连接焊盘8的中心与半导体的中心的线垂直的线 封装2，而不是将焊盘8的中心与半导体封装2的中心连接的线。

公开(公告)号：US20050128721A1

公开(公告)日：2005-06-16

申请号：US10735638

申请日：2003-12-16

Applicant: Cheng Tay ,  Wendy Chet Ngoh ,  Choi Chan

Inventor： Cheng Tay ,  Wendy Chet Ngoh ,  Choi Chan

IPC: H05K1/11 ,  H05K7/06

CPC classification number: H05K1/111 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/09481 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/5313

Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.

Abstract translation: 印刷电路板包括适合于焊接到装置的相应组焊球的一组焊盘。 该组的每个焊盘在其焊接球被焊接到该焊盘之后预期在焊球上的裂纹开始的位置处具有在其周边上的裂纹起始点。 对于具有位于其中的微孔的该组的垫，该微孔的中心位于比该垫的中心更远离其裂纹起始点。 对于具有沿着其周边的一部分的轨迹合并的该组的焊盘，该部分不包括该裂纹起始点的附近。

公开(公告)号：US20030060062A1

公开(公告)日：2003-03-27

申请号：US10247393

申请日：2002-09-19

Applicant: Olympus Optical Co., Ltd.

Inventor： Sumito Honda ,  Takashi Suzuki

IPC: H05K001/00

CPC classification number: H05K1/111 ,  H05K1/189 ,  H05K3/281 ,  H05K3/3442 ,  H05K2201/09254 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611

Abstract: On the surface of a flexible printed circuit board according to the present invention, at least one conductive land formed of a conductive pattern for mounting a component thereon which is to be mounted on the flexible printed circuit board, at least one first conductor line lead formed of another conductive pattern which extends from the conductor land and which forms an electrical connection of the conductor land, at least one second conductor line lead formed of another conductive pattern which extends in a direction orthogonal to the first conductor line lead and which extends from the conductor land for forming an electrical connection of the conductor land, and at least one semi-circular conductor line for electrically connecting the end of the first conductor line lead and the end of the second conductor line lead are formed.

Abstract translation: 在根据本发明的柔性印刷电路板的表面上，由用于安装其上的部件的导电图案形成的至少一个导电接合面将安装在柔性印刷电路板上，形成至少一个第一导体线引线 从导体焊盘延伸并且形成导体焊盘的电连接的另一个导电图案，至少一个第二导线引线，其由与第一导线引线正交的方向延伸的另一个导体图形形成， 形成用于形成导体焊盘的电连接的导体焊盘，以及用于电连接第一导线引线的端部和第二导线引线的端部的至少一个半圆导体线。

公开(公告)号：US20020014683A1

公开(公告)日：2002-02-07

申请号：US09912887

申请日：2001-07-25

Applicant: NEC Corporation

Inventor： Michihiko Ichinose

IPC: H01L023/495

CPC classification number: H05K3/3436 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/28 ,  H05K2201/09263 ,  H05K2201/09281 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes an interposing substrate having a top surface mounting thereon a semiconductor chip and a bottom surface mounting thereon a solder ball islands. Chip electrodes of the semiconductor chip are connected to the solder ball islands through a top interconnect pattern, via holes and a bottom interconnect pattern. The second interconnect pattern has a solder-flow damping/stopping pattern in the vicinity of the solder ball islands for stopping the solder from flowing onto the bottom interconnect pattern upon melting.

Abstract translation: 半导体器件包括其上安装有半导体芯片的顶表面和其上安装有焊球岛的底表面的中介衬底。 半导体芯片的芯片电极通过顶部互连图案，通孔和底部互连图案连接到焊球岛。 第二互连图案在焊球附近具有焊料流阻尼/停止图案，用于在熔化时阻止焊料流到底部互连图案上。

公开(公告)号：EP3232743A1

公开(公告)日：2017-10-18

申请号：EP15866432.6

申请日：2015-12-08

Applicant: Fujikura, Ltd.

Inventor： OGURA, Shingo ,  HAMMURA, Tetsu

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0283 ,  H05K1/0271 ,  H05K1/0281 ,  H05K1/118 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/09845 ,  H05K2201/0989 ,  H05K2201/10522

Abstract: A stretchable board is configured to include: a base material (10) having stretchability; a first and second electronic components (20 and 30) mounted on the base material (10); a wire (40) arranged on the base material (10); and a first and second connectors (50A and 50B) for connecting the first and second electronic components (20 and 30) and the wire (40) to each other, in which at least a portion of the first electronic component (20) and at least a portion of the second electronic component (30) face each other in a planned stretching direction (D) in which the base material (10) includes: a facing zone (Z1) interposed between the first and second electronic components (20 and 30) in a planned stretching direction (D) and a non-facing zone (Z2) other than the facing zone (Z1) on the base material (10), in which at least a portion of the first connector (50A) or at least a portion of the second connector (50B) are arranged in the non-facing zone (Z2), and in which at least one of the wires (40) is arranged in the non-facing zone (Z2).

Abstract translation: 伸缩性板构成为具有：具有伸缩性的基材（10） 安装在基材（10）上的第一和第二电子元件（20和30）; 布置在所述基底材料（10）上的导线（40）; 以及用于将第一和第二电子元件（20和30）与导线（40）彼此连接的第一和第二连接器（50A和50B），其中第一电子元件（20）的至少一部分和 所述第二电子部件（30）的至少一部分在所述基材（10）具有包含所述第一电子部件（20）和所述第二电子部件（30）之间的相对区域（Z1）的预定拉伸方向（D） ）在所述基材（10）上沿着预定的拉伸方向（D）和除所述面对区域（Z1）之外的非面向区域（Z2）形成，其中所述第一连接器（50A）的至少一部分或 第二连接器50B的一部分布置在非面对区域Z2中，并且其中至少一个导线40布置在非面对区域Z2中。

公开(公告)号：EP2529607A2

公开(公告)日：2012-12-05

申请号：EP11704856.1

申请日：2011-01-31

Applicant: Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO

Inventor： VAN HECK, Gerardus Titus ,  DE KOK, Margaretha Maria ,  VAN DEN BRAND, Jeroen

IPC: H05K3/32 ,  H05K3/36 ,  A41D1/00 ,  A41D27/08 ,  H01R13/62

CPC classification number: H05K1/0277 ,  G09F9/00 ,  G09F19/22 ,  H01L27/3293 ,  H01L31/0392 ,  H01L31/042 ,  H01L51/5203 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01R4/04 ,  H01R4/70 ,  H01R12/7076 ,  H05B33/0896 ,  H05B33/10 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/147 ,  H05K1/189 ,  H05K3/321 ,  H05K3/325 ,  H05K3/365 ,  H05K13/04 ,  H05K2201/029 ,  H05K2201/0311 ,  H05K2201/046 ,  H05K2201/083 ,  H05K2201/09081 ,  H05K2201/09281 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10484 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An assembly of a plurality of tiles (1) with a carrier (40). The tiles (1) comprise a foil (20) with an electro-physical transducer (10) and electrical connectors (24, 28) to said transducer. The tiles are mechanically and electrically coupled to the carrier in a connection portion (1c) of said tiles.

公开(公告)号：EP2529606A1

公开(公告)日：2012-12-05

申请号：EP11704488.3

申请日：2011-01-31

Applicant: Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO

Inventor： VAN DEN BRAND, Jeroen ,  VAN HECK, Gerardus Titus ,  DE KOK, Margaretha Maria

IPC: H05K1/18 ,  H05K3/32 ,  F21V21/096 ,  H01L31/045 ,  H01R13/62

CPC classification number: H05K1/0277 ,  G09F9/00 ,  G09F19/22 ,  H01L27/3293 ,  H01L31/0392 ,  H01L31/042 ,  H01L51/5203 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01R4/04 ,  H01R4/70 ,  H01R12/7076 ,  H05B33/0896 ,  H05B33/10 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/147 ,  H05K1/189 ,  H05K3/321 ,  H05K3/325 ,  H05K3/365 ,  H05K13/04 ,  H05K2201/029 ,  H05K2201/0311 ,  H05K2201/046 ,  H05K2201/083 ,  H05K2201/09081 ,  H05K2201/09281 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10484 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An assembly of a plurality of tiles (1) with a carrier (40). The tiles (1) comprise a foil (20) with an electro-physical transducer (10) and electrical connectors (24, 28) to said transducer. The tiles are mechanically and electrically coupled to the carrier in a connection portion (1c) of said tiles.

公开(公告)号：EP2059100B1

公开(公告)日：2011-09-28

申请号：EP07744769.6

申请日：2007-06-06

Applicant: Nippon Mektron, Limited

Inventor： MIYAHARA, Seiichiro, Nippon Mektron, Ltd.

IPC: H05K1/02

CPC classification number: H05K1/025 ,  H05K1/028 ,  H05K2201/09263 ,  H05K2201/09281

Abstract: Provided is a flexible wiring board, which reduces an impedance mismatch even if three-dimensionally folded, so that it can realize a reduction in a transmission loss. The flexible wiring board (10) includes a characteristic impedance control circuit (20), and is characterized in that the shape of a top plan projection of a folding portion (20A) of the characteristic impedance control circuit, after the portion (20A) is folded, may take an arcuate shape along a tangential line.

公开(公告)号：EP2086293A1

公开(公告)日：2009-08-05

申请号：EP08254167.3

申请日：2008-12-29

Applicant: Hon Hai Precision Industry Co., Ltd.

Inventor： Lin, Yu-Hsu ,  Wu, Jeng-Da ,  Chao, Chih-Hang

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0366 ,  H05K1/0245 ,  H05K1/0248 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09281

Abstract: A printed circuit board includes a base (40) and a signal trace (47) formed on the base. The signal trace includes a plurality of straight line segments (C1,C2,C3,C4) parallel to the first fibers (41). The signal trace is formed on the base in such a manner that the line segments partially superpose the first fibers (41) and partly superpose gap between adjacent first fibers.

Abstract translation: 印刷电路板包括基座（40）和形成在基座上的信号迹线（47）。 信号迹线包括平行于第一光纤（41）的多个直线段（C1，C2，C3，C4）。 信号迹线以这样的方式形成在基座上，即线段部分地叠置第一光纤（41）并部分地叠置相邻第一光纤之间的间隙。

公开(公告)号：EP1986479A3

公开(公告)日：2009-08-05

申请号：EP08153463.8

申请日：2008-03-27

Applicant: Omron Corporation

Inventor： Nagashima, Atsushi c/o Omron Corporation

IPC: H05K3/34 ,  G01R15/14

CPC classification number: H05K3/3421 ,  G01R1/203 ,  H05K1/111 ,  H05K3/222 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09909 ,  H05K2203/0465 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613

Abstract: An object of the present invention is to provide a wiring substrate capable of accurately detecting a potential difference in a shunt resistor and a current to be detected without being influenced by soldering, and a current detection device. A land mounted with a rectangular surface at each end of a shunt resistor is configured by first and second lands each having a rectangular portion and being arranged at a predetermined interval with a central line as a center, and third and fourth lands each having an area smaller than those of the first and second lands and being arranged at one end of the first and second lands to be connected respectively to the first and second lands. A wiring pattern for detecting a potential difference between the both ends of the shunt resistor is configured by a first wiring pattern connected to the third land and pulled out from the third land towards the fourth land, a second wiring pattern connected to the fourth land and pulled out from the fourth land towards the third land, and third and fourth wiring patterns connected respectively to the first and second wiring patterns and pulled out into one direction.