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    METHOD FOR FABRICATING A SELF-LIMITING SILICON BASED INTERCONNECT FOR TESTING BARE SEMICONDUCTOR DICE
    183.
    发明申请
    METHOD FOR FABRICATING A SELF-LIMITING SILICON BASED INTERCONNECT FOR TESTING BARE SEMICONDUCTOR DICE 审中-公开
    一种用于测试半导体半导体的自限制硅基互连的方法

    公开(公告)号：WO1996014660A1

    公开(公告)日：1996-05-17

    申请号：PCT/US1995014483

    申请日：1995-11-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  AKRAM, Salman ,  FARNWORTH, Warren, M. ,  WOOD, Alan, G.

    IPC: H01L21/66

    CPC classification number: G01R1/06738 ,  G01R1/07314 ,  H01L2224/13019 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10T29/49155 ,  Y10T29/49453

    Abstract: A method for forming a self-limiting, silicon based interconnect for making temporary electrical contact with bond pads on a semiconductor die is provided. The interconnect includes a silicon substrate having an array of contact members adapted to contact the bond pads on the die for test purposes (e.g., burn-in testing). The interconnect is fabricated by: forming the contact members on the substrate; forming a conductive layer on the tip of the contact members; and then forming conductive traces to the conductive layer. The conductive layer is formed by depositing a silicon containing layer (e.g., polysilicon, amorphous silicon) and a metal layer (e.g., titanium, tungsten, platinum) on the substrate and contact members. These layers are reacted to form a silicide. The unreacted metal and silicon containing layer are then etched selective to the conductive layer which remains on the tip of the contact members. Conductive traces are then formed in contact with the conductive layer using a suitable metallization process. Bond wires are attached to the conductive traces and may be attached to external test circuitry. Alternately, another conductive path such as external contacts (e.g., slide contacts) may provide a conductive path between the conductive traces and external circuitry. The conductive layer, conductive traces and bond wires provide a low resistivity conductive path from the tips of the contact members to external test circuitry.

    Abstract translation: 提供一种用于形成用于与半导体管芯上的接合焊盘暂时电接触的自限制硅基互连的方法。 互连包括具有适于接触芯片上的接合焊盘的接触部件阵列的硅衬底用于测试目的（例如，老化测试）。 互连通过以下方式制造：在衬底上形成接触构件; 在所述接触构件的尖端上形成导电层; 然后在导电层上形成导电迹线。 通过在衬底和接触构件上沉积含硅层（例如，多晶硅，非晶硅）和金属层（例如，钛，钨，铂）形成导电层。 这些层反应形成硅化物。 然后将未反应的含金属和含硅层选择性地蚀刻到保留在接触构件的尖端上的导电层。 然后使用合适的金属化工艺将导电迹线形成为与导电层接触。 接合线连接到导电迹线，并且可以附接到外部测试电路。 或者，诸如外部触点（例如，滑动触点）的另一导电路径可以在导电迹线和外部电路之间提供导电路径。 导电层，导电迹线和接合线提供从接触构件的尖端到外部测试电路的低电阻率导电路径。

    PROCESS FOR PRODUCING A FLAT CONNECTION
    185.
    发明申请
    PROCESS FOR PRODUCING A FLAT CONNECTION 审中-公开
    生产平面连接的方法

    公开(公告)号：WO1990010320A1

    公开(公告)日：1990-09-07

    申请号：PCT/FR1990000137

    申请日：1990-02-27

    Applicant: THOMSON-BRANDT ARMEMENTS ,  BANSARD, Joël

    Inventor： THOMSON-BRANDT ARMEMENTS

    IPC: H01R09/07

    CPC classification number: H05K3/4007 ,  H01R13/22 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2203/0307 ,  H05K2203/0723

    Abstract: The aim of the process is to improve flat connections, with a view to considerably reducing the contact resistance of the latter, which is generally high due to flaws in the surface flatness of the conducting ranges facing one another. The process consists in forming on a first conducting range (10) designed to enter into contact in a flat connection with a second conducting range, a surface state containing a plurality of studs (12) uniformly distributed, then in applying opposite each other and clamping together the two ranges so as to establish a contact between each stud and the second range. Applications: particularly interesting for high voltage connections and very high frequency and ultrahigh frequency ''strip line'' connections.

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