公开(公告)号：WO01039332A1

公开(公告)日：2001-05-31

申请号：PCT/US1999/027868

申请日：1999-11-24

IPC: H01R13/648 ,  H01R12/72 ,  H01R13/646 ,  H01R13/6471 ,  H01R13/6473 ,  H01R24/00 ,  H01R24/44 ,  H05K1/02 ,  H05K1/11 ,  H05K3/04 ,  H05K3/42 ,  H05K7/06 ,  H01R12/16 ,  H01R12/18

CPC classification number: H01R12/724 ,  H01R12/727 ,  H01R13/6471 ,  H01R13/6473 ,  H01R13/6587 ,  H01R24/44 ,  H05K1/0237 ,  H05K1/115 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189

Abstract: An electrical connector for transferring a plurality of differential signals between electrical components (14, 16). The connector is made of modules (18) that have a plurality of pairs (104) of signal conductors (102) with a first signal path and a second signal path. Each signal path has a pair of contact sections (116) extending between the contact portions. For each pair of signal conductors, a first distance between the interim sections is less than a second distance between the pair of signal conductors and any other pair of signal conductors of the plurality. Embodiments are shown that increase routability.

Abstract translation: 一种用于在电气部件（14,16）之间传送多个差分信号的电连接器。 连接器由具有多个具有第一信号路径和第二信号路径的多个信号导体对（104）的模块（18）组成。 每个信号路径具有在接触部分之间延伸的一对接触部分（116）。 对于每对信号导体，中间部分之间的第一距离小于一对信号导体与多个信号导体中的任何另外的一对信号导线之间的第二距离。 示出了增加可布线性的实施例。

公开(公告)号：WO99025164A1

公开(公告)日：1999-05-20

申请号：PCT/US1998/022378

申请日：1998-10-22

IPC: H05K1/14 ,  H05K3/00 ,  H05K7/14

CPC classification number: H05K7/1439 ,  H05K1/14 ,  H05K3/0064 ,  H05K7/1452 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2203/1147

Abstract: In one form, the invention is directed to the combination of: a plate; a first connector on the plate; a first circuit card assembly including a first circuit card and a second connector on the first circuit card which second connector is capable of coupling to the first connector; and a layer of sealing material on the plate and having a first opening therein to accept a part of the first circuit card assembly with the first and second connectors coupled. The layer of sealing material has a first cantilevered flap which has a first, relaxed state. The first cantilevered flap is deflected from the first state into a second state wherein the first cantilevered flap bears sealingly against a part of the first circuit card assembly with the first and second connectors coupled.

Abstract translation: 在一种形式中，本发明涉及：板的组合; 板上的第一连接器; 第一电路卡组件，包括第一电路卡和第二连接器，第一电路卡上的第二连接器能够耦合到第一连接器; 以及在所述板上的一层密封材料，并且在其中具有第一开口，以接纳所述第一和第二连接器连接的第一电路卡组件的一部分。 密封材料层具有第一悬臂翼片，其具有第一松弛状态。 第一悬臂翼片从第一状态偏转到第二状态，其中第一悬臂翼片密封地抵靠第一和第二连接器连接的第一电路卡组件的一部分。

公开(公告)号：WO99022552A1

公开(公告)日：1999-05-06

申请号：PCT/US1998/017397

申请日：1998-08-20

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K7/02

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09727

Abstract: A connector (400) for coupling high frequency signals between devices includes a substrate having an array of vias (410) for coupling a reference voltage to reference voltages traces (460) that extend along the substrate surface between the devices. Signal traces (430) including device pads (434) for coupling signals to and from the devices alternate with the reference voltage traces (460). The widths of the reference voltage traces (460) are varied to maintain a substantially constant separation between the reference voltage trace (460) and an adjacent signal trace (430).

Abstract translation: 用于在器件之间耦合高频信号的连接器（400）包括具有通孔阵列（410）的衬底，用于将参考电压耦合到沿器件之间的衬底表面延伸的参考电压迹线（460）。 包括用于将信号耦合到器件的器件焊盘（434）的信号迹线（430）与参考电压迹线（460）交替。 改变参考电压迹线（460）的宽度以保持参考电压迹线（460）和相邻信号迹线（430）之间的基本上恒定的间隔。

公开(公告)号：WO1997039608A1

公开(公告)日：1997-10-23

申请号：PCT/US1997006113

申请日：1997-04-11

Applicant: ARIZONA DIGITAL, INC.

Inventor： ARIZONA DIGITAL, INC. ,  BERDING, Andrew, R.

IPC: H05K01/14

CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/09263

Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. In one embodiment of the invention, a set of common points (23, 24) is electrically coupled to the connectors by individual conductive traces between each common point (23) and the corresponding pins (31-36) of the connectors. The common points are preferably centrally located among the plurality of connectors to reduce propagation delay. A connector (75) can be attached at the common points. The traces are separated from each other by lateral displacement in a single plane. If the backplane is a multi-layered printed circuit board, the traces are separated from each other by vertical displacement between the layers of the printed circuit board or by both vertical and horizontal displacement. The traces to the connectors nearest the common points (83) have a minimum length (96) greater than the distance (92) between the nearest connectors and the common points.

Abstract translation: 数据处理系统包括通过多个连接器连接到背板的背板和多个逻辑板。 在本发明的一个实施例中，一组公共点（23,24）通过连接器的每个公共点（23）和对应的引脚（31-36）之间的各个导电迹线电耦合到连接器。 公共点优选地位于多个连接器之间，以减少传播延迟。 连接器（75）可以​​在公共点附接。 通过在单个平面中的横向位移，迹线彼此分离。 如果背板是多层印刷电路板，则通过印刷电路板的层之间的垂直位移或垂直和水平位移两者彼此分开。 到最接近公共点（83）的连接器的迹线具有比最近连接器和公共点之间的距离（92）更大的最小长度（96）。

公开(公告)号：WO1993020673A1

公开(公告)日：1993-10-14

申请号：PCT/AU1993000144

申请日：1993-04-02

Applicant: JANIAK HOLDINGS PTY. LTD. ,  JANIAK, Andrew

Inventor： JANIAK HOLDINGS PTY. LTD.

IPC: H05K01/14

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  G06F13/409 ,  H05K1/117 ,  H05K1/14 ,  H05K3/0058 ,  H05K7/1461 ,  H05K2201/044 ,  H05K2201/10598

Abstract: A circuit board comprises a carrier board which functions as a base structure to which is attached rigidly at least one electronics components card to form a wafer assembly where edge connectors to the components card are free for access, said card being attached to the carrier board by at least two rigid mechanical connectors for example glued plastic fasteners/screws or bolts, nuts and spacer means to maintain the carrier board and card at a selected separation.

Abstract translation: 电路板包括作为基底结构的载体板，其刚性地附接至少一个电子部件卡，以形成其中组件卡的边缘连接器可自由进入的晶片组件，所述卡通过 至少两个刚性机械连接器，例如胶合塑料紧固件/螺钉或螺栓，螺母和间隔装置，以将承载板和卡保持在选定的间隔。

公开(公告)号：WO1989004587A1

公开(公告)日：1989-05-18

申请号：PCT/DE1988000685

申请日：1988-11-05

Applicant: SYSTEM KONTAKT GESELLSCHAFT FÜR ELEKTRONISCHE ... ,  LEITL, Franz

Inventor： SYSTEM KONTAKT GESELLSCHAFT FÜR ELEKTRONISCHE ...

IPC: H05K01/14

CPC classification number: H05K1/0228 ,  H05K1/0219 ,  H05K1/0245 ,  H05K9/0039 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/097

Abstract: A computer bus comprises conductive tracks which extend in four layers. Each plug-in point (I, II, III) has three columns (a, b, c) of plug-in holes arranged in a plurality of rows (1, 2, 3, ...). The conductive track which links the plug-in holes having the index a2 in sequence passes between the plug-in points I and II through the first layer, but between the points II and III through the fourth layer. The same principle applies to the conductive track which connects plug-in holes diagonally adjacent to the plug-in holes a2 or the second holes thereafter. The conductive tracks which connect the adjacent holes to the plug-in holes a2 pass through the fourth layer when the conductive track connecting the plug-in holes a2 in sequence passes through the first layer, and vice-versa. This ensures that the conductive tracks starting from neighbouring holes are situated a maximum distance apart. The adjacent conductive tracks which pass through the same layer lead to non-adjacent plug-in holes, which results in minimal signal coupling. In addition, the alternation between the layers leaves sufficient space in each layer for a protective grid, which further improves the decoupling and shielding of the signals transmitted by the bus. Since the alternation of the conducting tracks between the layers is carried out according to the same principle, all the conducting trucks have the same length. This enables signals with identical transmission times to be obtained. A series inductance is also provided for each transverse capacitor in such a way that signals of different frequencies travel at the same speed.

公开(公告)号：WO1983002521A1

公开(公告)日：1983-07-21

申请号：PCT/US1983000039

申请日：1983-01-12

Applicant: ELXSI

Inventor： ELXSI ,  HOLBERT, Kenneth, Wayne ,  MASSEY, Edwin, Michael

IPC: H01B07/08

CPC classification number: H02G5/005 ,  H05K1/0263 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/044 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09845 ,  H05K2201/10272

Abstract: A backplane power distribution system for making connections to the power planes of a computer system and having the capability of handling very high levels of current. This is achieved with a stepped backplane construction (17b-e). For example, in a multiple layer system having, in order, a first conductive layer (10a), a first dielectric layer (12a, 12b), a second conductive layer (10b), a second dielectric layer (12bc), and so on, each successive conductive and dielectric layers extend transversely beyond the preceding layers to present a substantial exposed area on all but the first conductive layer (17b-e). Typically, rectangular metal bus bars (not shown) are bolted to the backplane using plated through holes (20b-e) to make contact with the exposed areas (17b-e). Holes through the layers are provided and prepared such that each hole (15, 20 and 22) may make contact with a particular conductive layer as desired or in the case of ground with all ground conductive layers. Conductive layers (10a) and (10i) may be used as signal layers utilizing traces (14) and holes (15) while layers (10b-h) are so-called power planes.

Abstract translation: 背板配电系统，用于连接到计算机系统的电力平面，并且具有处理非常高水平的电流的能力。 这是通过阶梯式背板结构（17b-e）实现的。 例如，在依次具有第一导电层（10a），第一介电层（12a，12b），第二导电层（10b），第二介电层（12bc）等）的多层系统中 ，每个连续的导电和电介质层横向延伸超过先前的层，以在除第一导电层（17b-e）之外的所有部分上呈现基本的暴露区域。 通常，使用电镀通孔（20b-e）将矩形金属汇流条（未示出）螺栓连接到背板以与暴露区域（17b-e）接触。 提供并准备穿过这些层的孔，使得每个孔（15,20和22）可根据需要与特定的导电层接触，或者在所有接地导电层接地的情况下。 导电层（10a）和（10i）可以用作利用迹线（14）和孔（15）的信号层，而层（10b-h）是所谓的电源层。

公开(公告)号：WO1980001628A1

公开(公告)日：1980-08-07

申请号：PCT/US1980000088

申请日：1980-01-30

Applicant: TECHN MARKETING INC

Inventor： TECHN MARKETING INC ,  WELLS G

IPC: H01R23/68

CPC classification number: H05K1/14 ,  H01R12/79 ,  H05K1/148 ,  H05K2201/044 ,  H05K2201/0715

Abstract: The multi-layered back plane (100) permits a plurality of processors (200, 205, 210, 215) and a plurality of memories (220, 225) to be interleaved through separate memory interface boards (230A - 230H, 230AA - 230HH) in a computer in a manner which provides a significant reduction of path length while eliminating crossover of signal cables (40A - 40H) and permitting the use of identical memory interface boards, resulting in a significant increase in the clock rate and efficiency of the computer system.

公开(公告)号：KR101526318B1

公开(公告)日：2015-06-05

申请号：KR1020090002035

申请日：2009-01-09

Applicant: 삼성전자주식회사

Inventor： 박성주 ,  고기현 ,  성명희 ,  김수경

IPC: G06F13/00 ,  G11C7/10 ,  G06F1/00

CPC classification number: H05K1/0246 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10159

Abstract: 메모리모듈상에스터브저항이제거된메모리보오드형성구조가개시된다. 그러한메모리보오드형성구조는, 메인보오드상에탑재되고메모리버스를통해메모리콘트롤러와전기적으로연결된모듈소켓들과; 복수의메모리칩들이탑재되며상기메모리콘트롤러에의해제어되기위해상기모듈소켓들에각기접속되는메모리모듈보오드와; 상기메모리모듈보오드와상기메인보오드사이의전기적연결구조가 T 브랜치구조로되도록하며, 상기메모리모듈보오드에대한스터브저항기능을수행하기위해상기모듈소켓들사이에서상기메인보오드상에분기적으로배치되는스터브저항어레이부를구비한다. 본발명의실시예적구성에따르면, 메모리모듈의스터브저항이제거되므로모듈제조코스트가절감되고보오드의탑재공간이증가되는효과가있다. 또한, 메인보오드상에서 T 브랜치구조를가짐에의해메모리억세스동작의스피드가개선되는이점이있다.

公开(公告)号：KR1020130114491A

公开(公告)日：2013-10-17

申请号：KR1020120036915

申请日：2012-04-09

Applicant: 엘에스산전 주식회사

Inventor： 안홍선

IPC: H01H69/01 ,  H05K1/02 ,  H05K1/14

CPC classification number: H02H7/20 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10295 ,  H01H69/01

Abstract: PURPOSE: A digital protective relay and a backplane grounding method thereof are provided to discharge effectively noises regardless of a material by inducing the noises into grounding copper via a grounding pin. CONSTITUTION: An electronic circuit (200) includes a backplane printed circuit board (100) for making mutual electromagnetic interference noises flow in an external grounding unit. The backplane printed circuit board includes a connecting pin (110) and a first grounding copper (120). The first grounding copper induces the mutual electromagnetic interference noises from the connecting pin to the external grounding unit.

Abstract translation: 目的：提供一种数字保护继电器及其背板接地方法，无论材料如何，通过将接地引脚引入铜接地，有效释放噪声。 构成：电子电路（200）包括用于在外部接地单元中使相互电磁干扰噪声流动的背板印刷电路板（100）。 背板印刷电路板包括连接销（110）和第一接地铜（120）。 第一个接地铜引起从连接引脚到外部接地单元的相互电磁干扰噪声。