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公开(公告)号：KR101267780B1
公开(公告)日：2013-06-07
申请号：KR1020110071009
申请日：2011-07-18
Applicant: 국민대학교산학협력단
Abstract: 비정질 산화물 반도체 박막 트랜지스터의 커패시턴스 모델링 방법 및 그 장치가 개시된다. 본 발명의 일 실시예에 따른 비정질 산화물 반도체 박막 트랜지스터의 커패시턴스 모델링 방법은 밴드갭 내 상태밀도(subgap DOS)에 속박되어 있는 전하밀도를 계산하는 단계; 게이트 전압의 기 설정된 범위에 따라 채널 내에 존재하는 전하밀도를 주요(dominant) 캐리어 성분으로 근사화하는 단계; 상기 근사화된 상기 전하밀도에 기초하여 단위면적당 총 전하를 계산하는 단계; 및 상기 밴드갭 내 상태밀도, 상기 계산된 상기 단위면적당 총 전하 및 기 입력된 복수의 파라미터들에 대한 정보에 기초하여 커패시턴스 모델을 생성하는 단계를 포함함으로써, 비정질 산화물 반도체 TFT 기반의 해석적인 커패시턴스 모델을 제공하고, 이를 통해 커패시턴스 계산 속도를 향상시켜 시뮬레이션 모델로 적용할 수 있다.
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公开(公告)号：KR1020130010518A
公开(公告)日：2013-01-29
申请号：KR1020110071009
申请日：2011-07-18
Applicant: 국민대학교산학협력단
CPC classification number: G06F17/5045 , G06F17/5009
Abstract: PURPOSE: A capacitance modeling method of an amorphous oxide semiconductor TFT and an apparatus thereof are provided to improve the calculating speed of the capacitance by indicating a capacitance model as an analytical formula. CONSTITUTION: An input unit(1010) receives information about a parameter. An approximating unit(1030) approximates electric charge density as a main carrier component according to the setting range of a gate voltage. A calculation unit(1020) calculates total charge by unit surface based on the approximated charge density. A capacitance model generator(1040) generates a capacitance model based on parameter information. [Reference numerals] (1010) Input unit; (1020) Calculation unit; (1030) Approximating unit; (1040) Capacitance model generator
Abstract translation: 目的：提供一种非晶氧化物半导体TFT的电容建模方法及其装置，通过将电容模型表示为分析公式来提高电容的计算速度。 构成：输入单元（1010）接收关于参数的信息。 近似单元（1030）根据栅极电压的设定范围近似电荷密度作为主载流子成分。 计算单元（1020）基于近似的电荷密度计算单位面积的总电荷。 电容模型发生器（1040）基于参数信息生成电容模型。 （附图标记）（1010）输入单元; （1020）计算单位; （1030）近似单位; （1040）电容模型发生器
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公开(公告)号：KR101105273B1
公开(公告)日：2012-01-17
申请号：KR1020110070958
申请日：2011-07-18
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786 , G02F1/136
CPC classification number: H01L22/14 , H01L22/12 , H01L29/7869
Abstract: PURPOSE: A current modeling method and apparatus of an amorphous oxide semiconductor thin film transistor are provided to improve a current calculation speed by supplying an analytical current model. CONSTITUTION: Charge density which is restricted in state density within a band gap is calculated(S310). The charge density is approximated to a major carrier component in case voltage between gate-sources is less than threshold voltage and is over than the threshold voltage(S320). Total electric charge per unit area is calculated(S330). The mobility of a channel which depends on gate voltage is calculated(S340). A first current model and a second current model are created(S350). A total current model is created using the first current model and the second current model(S360).
Abstract translation: 目的：提供非晶氧化物半导体薄膜晶体管的当前建模方法和装置，以通过提供分析电流模型来提高当前的计算速度。 构成：计算在带隙内的状态密度受限的电荷密度（S310）。 在栅极源之间的电压小于阈值电压并超过阈值电压时，电荷密度近似于主载流子分量（S320）。 计算每单位面积的总电荷（S330）。 计算取决于栅极电压的通道的迁移率（S340）。 创建第一个当前模型和第二个当前模型（S350）。 使用第一个当前模型和第二个当前模型创建总电流模型（S360）。
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公开(公告)号：KR101049298B1
公开(公告)日：2011-07-14
申请号：KR1020100045684
申请日：2010-05-14
Applicant: 국민대학교산학협력단
IPC: H01L21/8242 , H01L27/108 , H01L27/105
Abstract: PURPOSE: A method for manufacturing an SB DRAM cell transistor without a capacitor is provided to reduce a defect caused by inconsistency in gratings by alternately performing heterogeneous bonding of a silicon layer and a silicon germanium layer via a molecular beam epitaxy growth. CONSTITUTION: A wafer is etched by using a Damascene process(S200). The poly-crystal silicon is evaporated and a lower gate is formed(S300). A polycrystalline silicon layer is flattened through the chemical mechanical polishing process(S400). The silicon dioxide is evaporated, the silicon dioxide wall is made and the silicon dioxide wall is etched for channel forming(S500). The silicon channel layer crystallized between the silicon dioxide walls is evaporated and engraved through the chemical mechanical polishing(S600). The silicon channel layer is etched in order to make the rule grating(S700).
Abstract translation: 目的：提供一种用于制造没有电容器的SB DRAM单元晶体管的方法，以通过经由分子束外延生长交替地执行硅层和硅锗层的非均匀结合来减少由光栅不一致引起的缺陷。 构成：使用镶嵌工艺蚀刻晶片（S200）。 多晶硅蒸发并形成下部浇口（S300）。 通过化学机械抛光工艺使多晶硅层变平（S400）。 蒸发二氧化硅，制成二氧化硅壁，并蚀刻二氧化硅壁用于通道形成（S500）。 在二氧化硅壁之间结晶的硅沟道层被蒸发并通过化学机械抛光（S600）进行雕刻。 蚀刻硅沟道层以制造规则光栅（S700）。
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Patent Agency Ranking16.发明公开
公开(公告)号：KR1020150088086A
公开(公告)日：2015-07-31
申请号：KR1020140008467
申请日：2014-01-23
Applicant: 국민대학교산학협력단
IPC: G01N27/416 , G01N27/327 , G01N27/403
CPC classification number: G01N27/416 , G01N27/327 , G01N27/403
Abstract: 본발명은바이오센서및 감지방법에관한것으로, 보다상세하게는하향식(top-down approach) 제조공정을이용하여반도체소자로이루어진바이오센싱부와타겟물질의상태변수에상응하는전류신호를증폭하는증폭부가집적된바이오센서및 바이오물질감지방법에관한것이다. 본발명은상기와같은종래기술의문제점을해결하고자도출된것으로서, 하향식(top-down approach) 제조공정을이용하여바이오센서부분과증폭회로를단일계열의공정으로형성하고, 이로인하여바이오센서및 증폭회로의공정편차를줄일뿐 아니라바이오센서와증폭회로를단일칩 상에용이하게집적할수 있어소형화를달성할수 있는바이오센서및 바이오물질감지방법을제안하는것을목적으로한다.
Abstract translation: 本发明涉及一种生物传感器和生物感测方法，更具体地说，涉及一种生物传感器和生物传感方法，其中使用自顶向下制造方法的半导体器件制造的生物传感单元和放大 将对应于目标材料的状态变量的电流信号进行放大的单元进行积分。 本发明被扣除以解决传统技术的问题，并且旨在通过使用自上而下的方法通过单个系统的处理形成生物传感器部分和放大电路来减少生物传感器和放大电路的工艺偏差 并提出了通过在单个芯片上容易地将生物传感器和放大电路集成来实现最小化的生物传感器和生物传感方法。
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17.发明授权
公开(公告)号：KR101427714B1
公开(公告)日：2014-08-07
申请号：KR1020130135421
申请日：2013-11-08
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786
CPC classification number: H01L22/14 , H01L22/30 , H01L29/78663
Abstract: Disclosed are a method of extracting the surface potential and state density within a band-gap of an amorphous semiconductor thin film transistor using a coupling factor, and a device thereof. The method for extracting the surface potential of the amorphous semiconductor thin film transistor according to an embodiment of the present invention comprises a step of measuring a drain current by a gate voltage of the thin film transistor; a step of extracting a drain current lower than a threshold voltage between the measured drain currents; and a step of extracting the surface potential by the gate voltage of the thin film transistor based on the differentiation of the drain current extracted. The step of extracting the surface potential extracts the surface potential by the gate voltage in the light of a coupling factor included in the surface potential and the extracted drain currents.
Abstract translation: 公开了使用耦合因子提取非晶半导体薄膜晶体管的带隙内的表面电位和状态密度的方法及其装置。 根据本发明实施例的提取非晶半导体薄膜晶体管的表面电位的方法包括通过薄膜晶体管的栅极电压测量漏极电流的步骤; 提取低于测量的漏极电流之间的阈值电压的漏极电流的步骤; 以及基于所提取的漏极电流的微分，通过薄膜晶体管的栅极电压提取表面电位的步骤。 提取表面电位的步骤根据包括在表面电位和提取的漏极电流中的耦合因子，通过栅极电压提取表面电位。
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公开(公告)号：KR101378112B1
公开(公告)日：2014-03-26
申请号：KR1020130020316
申请日：2013-02-26
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786
CPC classification number: H01L22/12 , H01L29/78693
Abstract: Disclosed is a method for extracting state density in a band gap of an amorphous oxide semiconductor thin film transistor and a device for the same. The method for extracting state density in a band gap of an amorphous oxide semiconductor thin film transistor according to an embodiment of the present invention includes a step of measuring a drain current according to a gate voltage of the thin film transistor; a step of calculating an ideality factor according to the gate voltage by using the measured drain current; a step of differentiating the calculated ideality factor and obtaining a capacitance within a channel based on the differentiated ideality factor; and a step of extracting the state density within the band gap of the thin film transistor based on the obtained capacitance within the cannel. The step of calculating the ideality factor comprises: calculating the ideality factor based on the drain current which is less than or equal to a threshold voltage among the measured drain current so that the state density in the band gap can be extracted without a complex modification. The ideality factor is differentiated so that the accurate state density in the band gap, which is independent to the threshold voltage and is not influenced from heat, light, or temperature, can be extracted. [Reference numerals] (AA) START; (BB) END; (S310) Measuring drain current according to gate voltage; (S320) Calculating an ideal coefficient according to the gate voltage by using the measured drain current; (S330) Differentiating the calculated ideal coefficient; (S340) Obtaining capacitance in a channel based on the differentiated ideal coefficient; (S350) Extracting status density in a band gap based on the capacitance in the obtained channel
Abstract translation: 公开了一种用于提取非晶氧化物半导体薄膜晶体管的带隙中的状态密度的方法及其装置。 根据本发明实施例的用于提取非晶氧化物半导体薄膜晶体管的带隙中的状态密度的方法包括根据薄膜晶体管的栅极电压测量漏极电流的步骤; 通过使用测量的漏极电流来计算根据栅极电压的理想因子的步骤; 基于分解的理想因子，区分计算出的理想因子并获得信道内的电容的步骤; 以及基于所获得的所述容器内的电容提取所述薄膜晶体管的带隙内的状态密度的步骤。 计算理想因子的步骤包括：基于在测量的漏极电流中小于或等于阈值电压的漏极电流来计算理想因子，使得可以在不进行复杂修改的情况下提取带隙中的状态密度。 理想因素是有区别的，因此可以提取与阈值电压无关并且不受热，光或温度影响的带隙中的准确状态密度。 （附图标记）（AA）START; （BB）END; （S310）根据栅极电压测量漏极电流; （S320）使用测定的漏极电流，根据栅极电压计算理想系数; （S330）微分计算的理想系数; （S340）基于差分理想系数获得信道中的电容; （S350）基于获得的通道中的电容提取带隙中的状态密度
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公开(公告)号：KR101344754B1
公开(公告)日：2013-12-24
申请号：KR1020130027999
申请日：2013-03-15
Applicant: 국민대학교산학협력단
IPC: H01L21/66 , H01L29/786 , G02F1/136
CPC classification number: H01L22/12 , H01L22/30 , H01L29/78693
Abstract: A method for extracting the density of state within an intrinsic band gap of an amorphous oxide semiconductor thin film transistor and a device thereof are disclosed. The method for extracting the density of state within the intrinsic band gap of the amorphous oxide semiconductor thin film transistor according to the present invention comprises; a step of measuring darkroom capacitance according to gate voltage of a thin film transistor; a step of measuring light reaction capacitance of the thin film transistor by irradiating the thin film transistor with a light source of a predetermined wavelength; a step of applying a first capacitance model and a second capacitance model to an area under flat-band voltage of the thin film transistor and an area over the flat-band voltage of the thin film transistor; and a step of extracting the density of state of an acceptor within the band gap and the density of state of a donor within the band gap based on the darkroom capacitance, the light reaction capacitance, and the applied first and second capacitance models. The present invention extracts the whole density of state within the band gap using experimental measurement data and rapidly simply extracts the whole density of state within the band gap by omitting a repetitive process and a complex calculation. [Reference numerals] (AA) START;(BB) END;(S210) Darkroom capacitance according to gate voltage is measured in a darkroom;(S220) Light reaction capacitance according to gate voltage is measured by irradiating a light source;(S230) Different capacitance model is applied to an area under or over flat voltage (V_FB);(S240) Density of state of a donor within a band gap and the density of state of anacceptor within the band gap are separately extracted based on measured darkroom capacitance, light reaction capacitance, and a capacitance model
Abstract translation: 公开了一种用于提取非晶氧化物半导体薄膜晶体管的固有带隙内的状态密度的方法及其装置。 根据本发明的提取非晶氧化物半导体薄膜晶体管的本征带隙内的状态密度的方法包括： 根据薄膜晶体管的栅极电压测量暗室电容的步骤; 通过用预定波长的光源照射薄膜晶体管来测量薄膜晶体管的光反应电容的步骤; 将第一电容模型和第二电容模型应用于薄膜晶体管的平带电压下的区域和薄膜晶体管的平坦带电压上的面积的步骤; 以及基于暗室电容，光反应电容和所施加的第一和第二电容模型，提取带隙内的受体的状态密度和施加体在带隙内的状态密度的步骤。 本发明使用实验测量数据提取带隙内的整体状态密度，并且通过省略重复处理和复杂计算，快速简单地提取带隙内的整体状态密度。 （参考号）（AA）START;（BB）END;（S210）根据栅极电压的暗室电容在暗室中测量;（S220）通过照射光源测量根据栅极电压的光反应电容;（S230） 不同的电容模型应用于平坦电压（V_FB）以下的区域;（S240）基于测量的暗室电容，单独提取在带隙内的供体的状态密度和带隙内的受体的状态密度， 光反应电容和电容模型
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公开(公告)号：KR1020130046317A
公开(公告)日：2013-05-07
申请号：KR1020110110835
申请日：2011-10-27
Applicant: 국민대학교산학협력단
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/78696 , H01L29/06 , H01L29/78663
Abstract: PURPOSE: An amorphous semiconductor thin film transistor with an active layer doped with different concentrations and a manufacturing method thereof are provided to improve stability by making the doping concentration of a semiconductor layer different. CONSTITUTION: A gate is formed on a substrate. A gate insulating layer is formed on the gate. Semiconductor layers doped with different concentrations are laminated to form an active layer(140). A source(150) is in contact with the active layer. A drain(160) is in contact with the active layer.
Abstract translation: 目的：提供具有掺杂不同浓度的有源层的非晶半导体薄膜晶体管及其制造方法，以通过使半导体层的掺杂浓度不同而提高稳定性。 构成：在基板上形成栅极。 在栅极上形成栅极绝缘层。 掺杂不同浓度的半导体层被层压以形成有源层（140）。 源（150）与有源层接触。 漏极（160）与有源层接触。
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