公开(公告)号：KR1020150005289A

公开(公告)日：2015-01-14

申请号：KR1020130079055

申请日：2013-07-05

Applicant: 삼성전기주식회사

Inventor： 박미진 ,  크리스틴로메로

IPC: H05K3/46 ,  H05K3/40

Abstract: 본 발명은, 기판의 소형화, 경량화, 박형화를 위해, 일면에 회로배선층이 형성된 절연층의 반복 적층으로 이루어진 다층 인쇄회로기판에 있어서, 적어도 하나 이상의 절연층을 두께 방향으로 관통하여 형성된 비아전극; 상기 비아전극의 상부 또는 하부와 접속하는 비아패드; 및 적어도 하나 이상의 절연층을 사이에 두고 상기 비아패드와 대향하는 위치에 형성된 부하용 패드;를 포함하는, 다층 인쇄회로기판을 제시한다.

Abstract translation: 本发明提供一种多层印刷电路板，其通过反复层叠绝缘层而形成，每个绝缘层在其一侧包括电路布线层，用于减小多层印刷电路板的尺寸和重量，并使多层印刷电路板 印刷电路板。 多层印刷电路板包括：沿厚度方向穿过至少一个绝缘层的通孔电极; 通孔焊盘，其连接到所述通孔电极的上侧或下侧; 以及通过插入至少一个绝缘层而定位成面对通孔焊盘的负载焊盘。

公开(公告)号：KR101365281B1

公开(公告)日：2014-02-19

申请号：KR1020120103421

申请日：2012-09-18

Applicant: 삼성전기주식회사

Inventor： 이동환 ,  박승욱 ,  크리스틴로메로 ,  권영도 ,  김진구

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H03H7/17 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09381

Abstract: The present invention relates to a via structure with an open stub and a printed circuit board including the same. According to one embodiment of the present invention, suggested are the via structure with the open stub and the printed circuit board including the via with the open stub. Wherein, the via structure includes: a signal transmission via which passes through an insulation layer; top and bottom via pads which connect the signal transmission line to first and second transmission lines which are formed on the upper and lower sides of the insulation layer, respectively; and one or more open stubs which are connected to the outer circumference of each via pad to have shunt capacitance between ground patterns which are formed on the upper and lower sides of the insulation layer.

Abstract translation: 本发明涉及具有开口短截线的通孔结构和包括该通孔结构的印刷电路板。 根据本发明的一个实施例，提出了具有开放短截线和印刷电路板的通孔结构，其包括具有开口短管的通孔。 其中，通孔结构包括：穿过绝缘层的信号传输; 顶部和底部通孔焊盘，其分别将信号传输线连接到形成在绝缘层的上侧和下侧上的第一和第二传输线; 以及连接到每个通孔焊盘的外周的一个或多个开放短截线，以在形成在绝缘层的上侧和下侧的接地图案之间具有分流电容。

公开(公告)号：KR1020130135044A

公开(公告)日：2013-12-10

申请号：KR1020130032210

申请日：2013-03-26

Applicant: 삼성전기주식회사

Inventor： 박승욱 ,  크리스틴로메로 ,  이창배 ,  박미진

IPC: H01L23/48 ,  H01L21/60

Abstract: The present invention relates to a plug via lamination structure, a lamination substrate having a via lamination structure, and a manufacturing method thereof. The present invention comprises a penetration hole plating layer; a via plug; a circuit pattern; and a lamination conductive via. The penetration hole plating layer is plated on an inner surface of a penetration hole formed on a substrate at a predetermined thickness, and is plated around the upper and lower units of the penetration hole at a t-thickness. The via plug is formed inside the penetration hole plating layer. The via plug is exposed by enabling upper and lower units to penetrate the upper and lower units of the penetration hole plating layer. The circuit pattern is formed on the upper and lower units of the penetration hole plating layer and the via plug. The t'-thickness of the circuit pattern formed on the penetration hole plating layer is thicker than the t-thickness. The lamination conductive via penetrates a first insulating layer formed on the substrate and the circuit pattern, is formed in the via hole formed on the upper part of the penetration hole, and is formed on the upper part of the circuit pattern at α-thinkness. The present invention is satisfied with a formula T

Abstract translation: 本发明涉及一种插头通孔层叠结构体，具有通孔层叠结构的层压基板及其制造方法。 本发明包括穿孔镀层; 通孔塞 电路图案 和层压导电通孔。 将贯通孔镀层以规定的厚度电镀在形成于基板上的贯通孔的内表面上，以t的厚度镀在贯通孔的上下单元上。 通孔塞形成在贯通孔镀层的内部。 通过使上部和下部单元穿透穿透孔镀层的上部和下部单元来暴露通孔塞。 电路图案形成在贯通孔镀层和通孔塞的上下单元上。 形成在贯通孔镀层上的电路图案的t'厚度比t厚度厚。 层叠导电通孔穿透形成在基板上的第一绝缘层和电路图案，形成在形成在穿透孔的上部的通孔中，并且以α-思想形成在电路图案的上部。 本发明对公式T <= t'+α满足。 提供具有通孔层叠结构的层叠基板及其制造方法。

公开(公告)号：KR1020130060754A

公开(公告)日：2013-06-10

申请号：KR1020110126981

申请日：2011-11-30

Applicant: 삼성전기주식회사

Inventor： 박미진 ,  크리스틴로메로 ,  박승욱

IPC: H05K3/46 ,  H05K3/40 ,  H01L23/48

CPC classification number: H05K1/0298 ,  H01L2224/10 ,  H05K1/0237 ,  H05K3/4038 ,  H05K3/4644 ,  H05K2201/09681 ,  H05K2201/09972 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: PURPOSE: A printed circuit board and a manufacturing method thereof are provided to improve bonding reliability by providing a mesh pattern to any one of circuit layers for improving a bonding force between the circuit layers. CONSTITUTION: A first circuit layer(120) is laminated on a core layer(110). The first circuit layer includes a first circuit pattern(122) and a first insulation sheet(124). The first circuit pattern includes a mesh pattern(122a) and a solid pattern(122b). A second circuit layer(130) is laminated on the first circuit layer. The second circuit layer includes a second circuit pattern(132) and a second insulation sheet(134).

Abstract translation: 目的：提供一种印刷电路板及其制造方法，以通过将网格图案提供给任何一个电路层来提高接合可靠性，以改善电路层之间的结合力。 构成：第一电路层（120）层叠在芯层（110）上。 第一电路层包括第一电路图案（122）和第一绝缘片（124）。 第一电路图案包括网格图案（122a）和实心图案（122b）。 在第一电路层上叠层第二电路层（130）。 第二电路层包括第二电路图案（132）和第二绝缘片（134）。