公开(公告)号：KR100425463B1

公开(公告)日：2004-03-30

申请号：KR1020010055468

申请日：2001-09-10

Applicant: 삼성전자주식회사

Inventor： 최한메 ,  김성태 ,  박영욱 ,  김영선 ,  김기철 ,  박인성

IPC: H01L21/316

CPC classification number: H01L21/02356 ,  C23C16/405 ,  C23C16/452 ,  C23C16/56 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/31604

Abstract: A method of forming a dielectric film composed of metal oxide under an atmosphere of activated vapor containing oxygen. In the method of forming the dielectric film, a metal oxide film is formed on a semiconductor substrate using a metal organic precursor and O2 gas while the semiconductor substrate is exposed under activated vapor atmosphere containing oxygen, and then, the metal oxide film is annealed while the semiconductor substrate is exposed under activated vapor containing oxygen. The annealing may take place in situ with the formation of the metal oxide film, at the same or substantially the same temperature as the metal oxide forming, and/or at at least one of a different pressure, oxygen concentration, or oxygen flow rate as the metal oxide forming.

Abstract translation: 一种在含氧的活性蒸气气氛下形成由金属氧化物构成的介电膜的方法。 在形成电介质膜的方法中，使用金属有机前体和O 2气体在半导体衬底上形成金属氧化物膜，同时在含氧的活化蒸气气氛下暴露半导体衬底，然后，将金属氧化物膜退火 在含有氧的活化蒸汽下暴露半导体衬底。 退火可以在与形成金属氧化物的温度相同或基本相同的温度下和/或在不同的压力，氧气浓度或氧气流量中的至少一个下就地形成金属氧化物膜， 金属氧化物形成。

公开(公告)号：KR100421044B1

公开(公告)日：2004-03-04

申请号：KR1020010038160

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  유차영 ,  박영욱

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device is provided to prevent a leakage current on an interface between a dielectric layer and the second electrode layer so that the thickness of an equivalent oxide layer of the dielectric layer is reduced, by using polysilicon to form the first electrode of a lower electrode and by using a Ru layer to form the second electrode layer of an upper electrode wherein the Ru layer has a relatively high electrical barrier. CONSTITUTION: A silicon nitride layer(40) is formed on the lower electrode. A metal oxide dielectric layer(50) is formed on the silicon nitride layer opposite to the lower electrode. The dielectric layer is formed on the lower electrode. The upper electrode composed of the Ru layer is formed on the dielectric layer.

Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以防止介电层和第二电极层之间的界面上的泄漏电流，从而通过使用介电层的等效氧化物层的厚度减小 形成下电极的第一电极并通过使用Ru层来形成上电极的第二电极层，其中Ru层具有相对高的电阻挡。 构成：氮化硅层（40）形成在下电极上。 金属氧化物介电层（50）形成在与下电极相对的氮化硅层上。 介电层形成在下电极上。 在电介质层上形成由Ru层构成的上部电极。

公开(公告)号：KR1020030088750A

公开(公告)日：2003-11-20

申请号：KR1020020026616

申请日：2002-05-15

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  박영욱 ,  임헌형 ,  허형조

IPC: H01L21/31

Abstract: PURPOSE: A method for manufacturing a high integrated device is provided to be capable of forming a nitride layer having good step coverage at low temperature by using ALD(Atomic Layer Deposition). CONSTITUTION: A semiconductor substrate(100) is defined to a field region and an active region. A transistor(153) is formed on the substrate. A cobalt silicide layer(180a,180a') is selectively formed on the substrate and the transistor. A nitride layer(190) is formed on the entire surface of the resultant structure by ALD. An insulating layer(190a) is deposited on the nitride layer(190). A contact hole(196) is formed to expose the cobalt silicide layer and the field region by sequentially etching the insulating layer and the nitride layer. A metal contact film(197) is filled into the contact hole.

Abstract translation: 目的：提供一种制造高集成器件的方法，以便能够通过使用ALD（原子层沉积）在低温下形成具有良好阶梯覆盖的氮化物层。 构成：将半导体衬底（100）定义为场区域和有源区域。 晶体管（153）形成在衬底上。 选择性地在衬底和晶体管上形成硅化钴层（180a，180a'）。 通过ALD在所得结构的整个表面上形成氮化物层（190）。 绝缘层（190a）沉积在氮化物层（190）上。 通过依次蚀刻绝缘层和氮化物层，形成接触孔（196）以露出硅化钴层和场区。 金属接触膜（197）被填充到接触孔中。

公开(公告)号：KR1020020096798A

公开(公告)日：2002-12-31

申请号：KR1020010041165

申请日：2001-07-10

Applicant: 삼성전자주식회사

Inventor： 김영관 ,  박영욱 ,  이승환

IPC: H01L21/20

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/452 ,  C23C16/45534 ,  C23C16/45542 ,  C23C16/45553 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/316 ,  H01L21/31608

Abstract: PURPOSE: A method for forming a thin film including silicon by stacking atomic layers using tris-dimethyl-aminosilane is provided to form a Si3N4 layer and a SiO2 layer by using tris-dimethyl-aminosilane as a reactant. CONSTITUTION: A substrate(1) is loaded in a chamber. A chemical adhesion layer of tris-dimethyl-aminosilane is formed on a surface of the substrate(1) by absorbing chemically the first part of tris-dimethyl-aminosilane. The second part of tris-dimethyl-aminosilane are adhered on the chemical adhesion layer of tris-dimethyl-aminosilane. A purge process is performed in the chamber by using N2. The non-adhesive part of the chemical adhesion layer of tris-dimethyl-aminosilane are removed by the purge process. Ar including NH3 is introduced into the chamber. A Si3N4 layer(8) is formed on the substrate(1) by reacting NH3 with tris-dimethyl-aminosilane.

Abstract translation: 目的：提供通过使用三 - 二甲基氨基硅烷层叠原子层来形成包含硅的薄膜的方法，通过使用三 - 二甲基氨基硅烷作为反应物形成Si 3 N 4层和SiO 2层。 构成：将衬底（1）装载到腔室中。 通过化学吸收第一部分三 - 二甲基氨基硅烷，在基板（1）的表面上形成三 - 二甲基氨基硅烷的化学粘附层。 三甲基氨基硅烷的第二部分粘附在三 - 二甲基氨基硅烷的化学粘合层上。 通过使用N2在室中进行吹扫处理。 通过吹扫法除去三 - 二甲基氨基硅烷的化学粘合层的非粘合部分。 将包含NH 3的Ar引入室中。 通过使NH 3与三 - 二甲基氨基硅烷反应，在基板（1）上形成Si 3 N 4层（8）。

公开(公告)号：KR1020020061942A

公开(公告)日：2002-07-25

申请号：KR1020010003066

申请日：2001-01-19

Applicant: 삼성전자주식회사

Inventor： 김형준 ,  박영욱 ,  남병윤

IPC: H01L27/10

CPC classification number: H01L21/76831 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: PURPOSE: An interconnection of a semiconductor device for forming a self-align contact is provided to prevent a conductive layer pattern from being exposed in etching a contact hole, by forming a self-align contact hole regarding the conductive layer pattern while an insulation layer is left on the sidewall of the conductive layer pattern like a bit line. CONSTITUTION: The first insulation layer pattern is formed on a semiconductor substrate(100). The conductive layer pattern(107a) is formed on the first insulation layer pattern. The second insulation layer pattern(108a) is formed on the conductive layer pattern, having a width larger than that of the conductive layer pattern. The third insulation layer residue(110a) is formed on at least one sidewall of the conductive layer pattern, having a thickness corresponding to the difference of width between the second insulation layer pattern and the conductive layer pattern. A spacer(116) is formed on at least the sidewall of the third insulation layer residue and the first insulation layer pattern.

Abstract translation: 目的：提供用于形成自对准接触的半导体器件的互连，以防止在蚀刻接触孔时导电层图案暴露，通过形成关于导电层图案的自对准接触孔，同时绝缘层为 像位线一样留在导电层图案的侧壁上。 构成：第一绝缘层图案形成在半导体衬底（100）上。 导电层图案（107a）形成在第一绝缘层图案上。 第二绝缘层图案（108a）形成在导电层图案上，其宽度大于导电层图案的宽度。 第三绝缘层残留物（110a）形成在导电层图案的至少一个侧壁上，其厚度对应于第二绝缘层图案和导电层图案之间的宽度差。 至少在第三绝缘层残渣和第一绝缘层图案的侧壁上形成间隔物（116）。

公开(公告)号：KR1020020044422A

公开(公告)日：2002-06-15

申请号：KR1020000073807

申请日：2000-12-06

Applicant: 삼성전자주식회사

Inventor： 이승환 ,  김영관 ,  김동찬 ,  박영욱

IPC: H01L21/20

CPC classification number: H01L21/0228 ,  C23C16/34 ,  C23C16/345 ,  C23C16/402 ,  C23C16/403 ,  C23C16/405 ,  C23C16/409 ,  C23C16/45531 ,  C23C16/45542 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/02274 ,  H01L21/3185

Abstract: PURPOSE: A method for fabricating a thin film by using an atomic layer deposition(ALD) method is provided to effectively prevent a particle source like NH4Cl from being generated when the second reaction gas necessary for forming the thin film is supplied, by purging byproducts after the first reaction gas is supplied and by supplying activated hydrogen gas to eliminate a halogen-group element combined with a semiconductor substrate. CONSTITUTION: The first reaction material containing the halogen-group element is supplied to the semiconductor substrate(100) so that the first reaction absorbing layer with which the halogen-group element is combined is chemically absorbed to the semiconductor substrate. The activated hydrogen gas(134) is supplied to the resultant structure having the first reaction absorbing layer to eliminate the halogen-group element from the first reaction absorbing layer. The second reaction material is supplied to the first reaction absorbing layer from which the halogen-group element is removed, so that the second reaction absorbing layer is chemically absorbed to form a solid thin film.

Abstract translation: 目的：提供一种通过使用原子层沉积（ALD）方法制造薄膜的方法，以有效地防止当形成薄膜所需的第二反应气体被供应时产生像NH 4 Cl这样的颗粒源， 提供第一反应气体并通过供给活化氢气来消除与半导体衬底结合的卤素基团元素。 构成：将包含卤素元素的第一反应材料供给到半导体基板（100），使得与卤素基元素组合的第一反应吸收层被化学吸收到半导体基板。 向具有第一反应吸收层的所得结构供给活化氢气（134），以从第一反应吸收层除去卤素基团元素。 将第二反应物质供给到除去卤素元素的第一反应吸收层，使第二反应吸收层被化学吸收而形成固体薄膜。

公开(公告)号：KR1020020010830A

公开(公告)日：2002-02-06

申请号：KR1020000044325

申请日：2000-07-31

Applicant: 삼성전자주식회사

Inventor： 최성제 ,  이승환 ,  형용우 ,  김영관 ,  박흥수 ,  박영욱

IPC: H01L27/108

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device is provided to prevent a cylindrical lower electrode from being damaged by a defect, by controlling a hemispherical grain(HSG) growth on the outer wall of the cylindrical lower electrode while minimizing damage to the cylindrical lower electrode. CONSTITUTION: A mold layer pattern exposing a predetermined region on a semiconductor substrate(100) is formed on the semiconductor substrate. The cylindrical lower electrode is formed in the predetermined region. An HSG growth control layer composed of polysilicon forms the outer wall of the lower electrode. A doped polysilicon layer forms the inner layer of the lower electrode. An HSG layer(136) constitutes the inner wall of the lower electrode, formed on the doped polysilicon layer. The mold layer pattern is eliminated. A dielectric layer(150) is formed on the lower electrode. An upper electrode(160) is formed on the dielectric layer.

Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以通过控制圆柱形下电极的外壁上的半球形晶粒（HSG）生长来防止圆柱形下电极被缺陷损坏，同时最小化对 圆柱形下电极。 构成：在半导体衬底上形成露出半导体衬底（100）上的预定区域的模层图案。 圆筒形下电极形成在预定区域中。 由多晶硅构成的HSG生长控制层形成下电极的外壁。 掺杂多晶硅层形成下电极的内层。 HSG层（136）构成形成在掺杂多晶硅层上的下电极的内壁。 消除模层图案。 在下电极上形成介电层（150）。 在电介质层上形成上电极（160）。

公开(公告)号：KR1020020005429A

公开(公告)日：2002-01-17

申请号：KR1020010038160

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  유차영 ,  박영욱

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device is provided to prevent a leakage current on an interface between a dielectric layer and the second electrode layer so that the thickness of an equivalent oxide layer of the dielectric layer is reduced, by using polysilicon to form the first electrode of a lower electrode and by using a Ru layer to form the second electrode layer of an upper electrode wherein the Ru layer has a relatively high electrical barrier. CONSTITUTION: A silicon nitride layer(40) is formed on the lower electrode. A metal oxide dielectric layer(50) is formed on the silicon nitride layer opposite to the lower electrode. The dielectric layer is formed on the lower electrode. The upper electrode composed of the Ru layer is formed on the dielectric layer.

Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以防止在电介质层和第二电极层之间的界面上的漏电流，使得电介质层的等效氧化物层的厚度通过使用 多晶硅以形成下部电极的第一电极，并且通过使用Ru层形成上部电极的第二电极层，其中Ru层具有较高的电气屏障。 构成：在下电极上形成氮化硅层（40）。 在与下电极相对的氮化硅层上形成金属氧化物电介质层（50）。 电介质层形成在下电极上。 由Ru层构成的上电极形成在电介质层上。

公开(公告)号：KR1020010084674A

公开(公告)日：2001-09-06

申请号：KR1020000009871

申请日：2000-02-28

Applicant: 삼성전자주식회사

Inventor： 임한진 ,  박흥수 ,  박기연 ,  박영욱

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a capacitor improving a leakage current characteristic by adding chrome is provided to improve a leakage current characteristic by handling a thickness of an oxide layer formed on a boundary between a storage electrode and a dielectric layer. CONSTITUTION: A storage electrode is formed on a semiconductor substrate. Chrome is supplied on the storage electrode by using a sputtering method or a CVD(Chemical Vapor Deposition) method or a spin-coating method. A metal oxide dielectric layer is formed on the storage electrode. A thermal process for the metal oxide dielectric layer is performed under an ultraviolet ray and ozone atmosphere. A high temperature thermal process for the metal oxide dielectric layer is performed under an oxygen atmosphere. An upper electrode is formed on the metal oxide dielectric layer.

Abstract translation: 目的：提供一种通过添加铬来制造提高漏电流特性的电容器的方法，以通过处理形成在存储电极和电介质层之间的边界上的氧化物层的厚度来改善泄漏电流特性。 构成：存储电极形成在半导体衬底上。 通过使用溅射法或CVD（化学气相沉积）法或旋涂法在存储电极上提供铬。 在存储电极上形成金属氧化物电介质层。 在紫外线和臭氧气氛下进行金属氧化物电介质层的热处理。 在氧气氛下进行金属氧化物介电层的高温热处理。 在金属氧化物电介质层上形成上电极。

公开(公告)号：KR1020010048683A

公开(公告)日：2001-06-15

申请号：KR1019990053469

申请日：1999-11-29

Applicant: 삼성전자주식회사

Inventor： 형용우 ,  박영욱 ,  이상협 ,  박흥수

IPC: H01L27/108

Abstract: PURPOSE: A method for manufacturing a capacitor storage electrode of a semiconductor device is provided to form the storage electrode suitable for a high integrated semiconductor capacitor, by maximizing an effective area of the capacitor storage electrode, and by simplifying a process for forming the storage electrode. CONSTITUTION: A conductive material is filled in a contact in which a predetermined region of a substrate(100) is exposed between word lines, to form a pad(112). The first etch stop layer is formed in a portion except the pad. After the second insulating layer(114) is deposited on the first etch stop layer and the pad, a bit line(116) is formed. After the bit line is formed, the second etch stop layer is formed. The third insulating layer filling a curved portion between bit lines is formed on the second etch stop layer. The fourth insulating layer(124) is deposited on the third insulating layer, and etched to form a storage electrode region by a photolithography process. A conductive material is deposited on the entire substrate including the fourth insulating layer to form a storage electrode layer. The storage electrode layer deposited on the surface of the fourth insulating layer is removed, and the fourth insulating layer is exposed to separate the storage electrode.

Abstract translation: 目的：提供一种用于制造半导体器件的电容器存储电极的方法，以通过最大化电容器存储电极的有效面积，并且简化用于形成存储电极的工艺来形成适用于高集成半导体电容器的存储电极 。 构成：导电材料填充在基板（100）的预定区域在字线之间露出的接触中，以形成焊盘（112）。 第一蚀刻停止层形成在除了焊盘之外的部分中。 在第二绝缘层（114）沉积在第一蚀刻停止层和焊盘上之后，形成位线（116）。 在形成位线之后，形成第二蚀刻停止层。 填充位线之间的弯曲部分的第三绝缘层形成在第二蚀刻停止层上。 第四绝缘层（124）沉积在第三绝缘层上，并通过光刻工艺进行蚀刻以形成存储电极区域。 在包括第四绝缘层的整个基板上沉积导电材料以形成存储电极层。 去除沉积在第四绝缘层的表面上的存储电极层，暴露第四绝缘层以分离存储电极。