公开(公告)号：KR100670916B1

公开(公告)日：2007-01-18

申请号：KR1020010037911

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 허형조 ,  강만석

IPC: H01L21/76

Abstract: 자기정렬된 셸로우 트렌치 소자분리 방법 및 이를 이용한 불휘발성 메모리 장치의 제조방법이 개시되어 있다. 반도체 기판 상에 산화막, 제1 도전층 및 저지막을 차례로 형성한다. 하나의 마스크를 사용하여 상기 저지막, 제1 도전층 및 산화막을 식각하여 산화막 패턴, 제1 도전층 패턴 및 저지막 패턴을 형성하고, 계속해서 상기 제1 도전층 패턴에 인접한 기판의 상부를 식각하여 트렌치를 형성한다. 어닐링을 실시하여 상기 제1 도전층 패턴의 측벽을 라운딩시킨 후, 상기 트렌치의 내면을 산화시켜 트렌치 내벽산화막을 형성한다. 상기 트렌치의 내부에 필드 산화막을 형성한다. 제1 도전층 패턴으로 이루어진 플로팅 게이트의 측벽이 포지티브 기울기를 갖는 것을 방지하여 후속하는 게이트 식각시 게이트 잔류물에 의해 소자의 전기적 불량이 유발되는 것을 방지할 수 있다.

公开(公告)号：KR1020020060453A

公开(公告)日：2002-07-18

申请号：KR1020010001555

申请日：2001-01-11

Applicant: 삼성전자주식회사

Inventor： 강만석 ,  허형조

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a polysilicon film of a semiconductor device and a method for forming a gate electrode of the semiconductor device by using the same are provided to form the polysilicon film without the morphology on a surface and to form the gate electrode having no pattern defect without the damage of a gate insulation film and the reduction of the reliability. CONSTITUTION: The polysilicon film(12) is formed on a base layer(10) by a CVD method or the thermal decomposition of a silicon base gas such as an SiH4 gas at the temperature above 660 deg.C. The results forming the polysilicon film is annealed at 600-900 deg.C for 1-2 minutes in order to remove the morphology(m) on the surface of the polysilicon film. Then, the dangling bond of the surface is almost joined or removed and the surface of the polysilicon film becomes smooth. The annealing process is carried out in a hydrogen atmosphere in order to block the generation of a natural oxide film on the surface.

Abstract translation: 目的：提供一种用于形成半导体器件的多晶硅膜的方法和通过使用该半导体器件形成半导体器件的栅电极的方法以形成多晶硅膜，而不形成表面的形态，并形成没有 图案缺陷，不会损坏栅极绝缘膜并降低可靠性。 构成：通过CVD法在基底层（10）上形成多晶硅膜（12），或者在高于660℃的温度下热分解硅基气体例如SiH 4气体。 形成多晶硅膜的结果在600-900℃下退火1-2分钟，以去除多晶硅膜表面的形态（m）。 然后，表面的悬挂键几乎接合或去除，并且多晶硅膜的表面变得光滑。 退火处理在氢气氛中进行，以阻止在表面上产生自然氧化膜。

公开(公告)号：KR1020020060451A

公开(公告)日：2002-07-18

申请号：KR1020010001553

申请日：2001-01-11

Applicant: 삼성전자주식회사

Inventor： 강만석 ,  허형조

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a gate electrode is provided to prevent the bad gate pattern on a photoresist process by improving the bad surface morphology of a polysilicon film. CONSTITUTION: An insulation film(110) and the polysilicon film are successively formed on a semiconductor substrate(100). The substrate having the insulation film and the polysilicon film is heat-treated in the hydrogen atmosphere. The gate electrode is formed by patterning the heat-treated insulation film and polysilicon film. The heat treatment is carried out under hydrogen atmosphere at 700-900 deg.C. A surface of the polysilicon film having the bad morphology is uniformed by the heat treatment. A photoresist film is formed on the polysilicon film(125) of good morphology. The gate pattern is formed by exposing and developing the photoresist. Because of the good surface morphology of the polysilicon film, the diffused reflection do not occur when exposing the photoresist film.

Abstract translation: 目的：提供一种用于形成栅电极的方法，以通过改善多晶硅膜的不良表面形态来防止光致抗蚀剂工艺上的不良栅极图案。 构成：在半导体衬底（100）上依次形成绝缘膜（110）和多晶硅膜。 具有绝缘膜和多晶硅膜的基板在氢气气氛中进行热处理。 栅极通过图案化经热处理的绝缘膜和多晶硅膜形成。 热处理在氢气氛下在700-900℃进行。 具有不良形态的多晶硅膜的表面通过热处理而均匀化。 在良好形貌的多晶硅膜（125）上形成光致抗蚀剂膜。 栅极图案通过曝光和显影光致抗蚀剂而形成。 由于多晶硅膜的良好的表面形态，当曝光光致抗蚀剂膜时，不会发生漫反射。

公开(公告)号：KR1020030088750A

公开(公告)日：2003-11-20

申请号：KR1020020026616

申请日：2002-05-15

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  박영욱 ,  임헌형 ,  허형조

IPC: H01L21/31

Abstract: PURPOSE: A method for manufacturing a high integrated device is provided to be capable of forming a nitride layer having good step coverage at low temperature by using ALD(Atomic Layer Deposition). CONSTITUTION: A semiconductor substrate(100) is defined to a field region and an active region. A transistor(153) is formed on the substrate. A cobalt silicide layer(180a,180a') is selectively formed on the substrate and the transistor. A nitride layer(190) is formed on the entire surface of the resultant structure by ALD. An insulating layer(190a) is deposited on the nitride layer(190). A contact hole(196) is formed to expose the cobalt silicide layer and the field region by sequentially etching the insulating layer and the nitride layer. A metal contact film(197) is filled into the contact hole.

Abstract translation: 目的：提供一种制造高集成器件的方法，以便能够通过使用ALD（原子层沉积）在低温下形成具有良好阶梯覆盖的氮化物层。 构成：将半导体衬底（100）定义为场区域和有源区域。 晶体管（153）形成在衬底上。 选择性地在衬底和晶体管上形成硅化钴层（180a，180a'）。 通过ALD在所得结构的整个表面上形成氮化物层（190）。 绝缘层（190a）沉积在氮化物层（190）上。 通过依次蚀刻绝缘层和氮化物层，形成接触孔（196）以露出硅化钴层和场区。 金属接触膜（197）被填充到接触孔中。

公开(公告)号：KR1020030065702A

公开(公告)日：2003-08-09

申请号：KR1020020005423

申请日：2002-01-30

Applicant: 삼성전자주식회사

Inventor： 임헌형 ,  형용우 ,  허형조 ,  유영섭

IPC: H01L29/788

Abstract: PURPOSE: A method for fabricating a floating gate type non-volatile memory device is provided to increase the capacitance between a floating gate electrode and a control gate electrode and enhance a coupling ratio by forming an insulating layer having a high dielectric constant between the floating gate electrode and the control gate electrode. CONSTITUTION: An isolation layer(6) is formed on a predetermined region of a semiconductor substrate(1) in order to define an active region. A tunnel oxide layer(2) and a floating gate line are sequentially stacked on an upper portion of the active region. A dielectric layer(9) including an insulating layer is formed on the entire surface of the semiconductor substrate including the floating gate line. A dielectric constant of the insulating layer is higher than the dielectric constant of a silicon nitride layer. A conductive layer of control gate is formed on the dielectric layer. A floating gate electrode(8a), the dielectric layer, and a control gate electrode(12) are formed by patterning sequentially the conductive layer of control gate, the dielectric layer, and the floating gate line.

Abstract translation: 目的：提供一种用于制造浮动栅型非易失性存储器件的方法，以增加浮栅和控制栅电极之间的电容，并通过在浮置栅极之间形成具有高介电常数的绝缘层来提高耦合比 电极和控制栅电极。 构成：为了限定有源区，在半导体衬底（1）的预定区域上形成隔离层（6）。 隧道氧化物层（2）和浮栅线依次层叠在有源区的上部。 在包括浮动栅极线的半导体衬底的整个表面上形成包括绝缘层的电介质层（9）。 绝缘层的介电常数高于氮化硅层的介电常数。 在电介质层上形成控制栅的导电层。 通过对控制栅极，电介质层和浮置栅极线的导电层顺序构图，形成浮栅电极（8a），电介质层和控制栅电极（12）。

公开(公告)号：KR1020030002352A

公开(公告)日：2003-01-09

申请号：KR1020010037911

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 허형조 ,  강만석

IPC: H01L21/76

Abstract: PURPOSE: A method for isolating a self-aligned shallow trench and a method for fabricating a non-volatile memory device by using the same are provided to form simultaneously a gate and an active region by using a self-aligned shallow trench isolation method. CONSTITUTION: An oxide layer is formed on a semiconductor substrate(100). The first conductive layer is formed on the oxide layer. A stopping layer is formed on the first conductive layer. A hard mask layer and an anti-reflective layer are formed on the stopping layer. A mask pattern is formed by etching the anti-reflective layer and the hard mask layer. A gate oxide layer(102), the first floating gate pattern(104), and a stopping layer pattern are formed by patterning the stopping layer, the first conductive layer, and the oxide layer. A trench(110) is formed by etching the substrate(100) neighboring to the first floating gate pattern(104). A sidewall of the first floating gate pattern(104) is rounded. A trench oxide layer is formed on an inner face of the trench(110). A field oxide layer is formed in the inside of the trench(110). The second floating gate pattern(118) is formed by removing a conductive layer of the field oxide layer. An ONO dielectric layer(120) is formed on the whole surface of the above structure. A control gate layer(122) is formed on the dielectric layer(120). A stack type gate structure is formed by etching the control gate layer(122), the dielectric layer(120), and the second floating gate pattern(118) and the first floating gate pattern.

Abstract translation: 目的：提供一种用于隔离自对准浅沟槽的方法和通过使用该方法制造非易失性存储器件的方法，以通过使用自对准浅沟槽隔离方法同时形成栅极和有源区域。 构成：在半导体衬底（100）上形成氧化物层。 第一导电层形成在氧化物层上。 在第一导电层上形成停止层。 在停止层上形成硬掩模层和抗反射层。 通过蚀刻抗反射层和硬掩模层形成掩模图案。 通过图案化阻挡层，第一导电层和氧化物层，形成栅氧化层（102），第一浮栅图案（104）和阻挡层图案。 通过蚀刻与第一浮栅图案（104）相邻的衬底（100）形成沟槽（110）。 第一浮栅图案（104）的侧壁是圆形的。 沟槽氧化物层形成在沟槽（110）的内表面上。 在沟槽（110）的内部形成场氧化物层。 通过去除场氧化物层的导电层来形成第二浮栅图案（118）。 在上述结构的整个表面上形成ONO电介质层（120）。 在电介质层（120）上形成控制栅层（122）。 通过蚀刻控制栅极层（122），电介质层（120）和第二浮栅图案（118）和第一浮栅图案来形成堆叠型栅极结构。

公开(公告)号：KR1020020096532A

公开(公告)日：2002-12-31

申请号：KR1020010035092

申请日：2001-06-20

Applicant: 삼성전자주식회사

Inventor： 권형신 ,  홍정인 ,  허형조

IPC: H01L21/76

Abstract: PURPOSE: A method for forming an active region having a rounded upper edge is provided to prevent a concentration phenomenon of electric field by rounding an upper edge portion of the active region. CONSTITUTION: A trench mask layer is formed on a semiconductor substrate(100). The trench mask layer is formed with a pad oxide layer, a silicon nitride layer, and a hard mask oxide layer. A trench mask pattern is formed by etching the trench mask layer. The trench mask pattern is formed with a hard mask oxide layer pattern, a silicon nitride layer pattern, and a pad oxide layer pattern. The first trench is formed by etching the semiconductor substrate(100). The second trench(150) is formed at a lower portion of the first trench by etching the semiconductor substrate(100). A recessed silicon nitride layer pattern(122) is formed by etching the silicon nitride layer pattern. A recessed pad oxide layer pattern(112) is formed by etching the pad oxide layer pattern. An edge(300) between an upper portion of an active region and a sidewall of the second trench(150) is rounded by performing an annealing process for the semiconductor substrate(100).

Abstract translation: 目的：提供一种用于形成具有圆形上边缘的有源区域的方法，以通过使有源区域的上边缘部分圆化来防止电场的浓度现象。 构成：在半导体衬底（100）上形成沟槽掩模层。 沟槽掩模层由衬垫氧化物层，氮化硅层和硬掩模氧化物层形成。 通过蚀刻沟槽掩模层形成沟槽掩模图案。 沟槽掩模图案由硬掩模氧化物层图案，氮化硅层图案和衬垫氧化物层图案形成。 通过蚀刻半导体衬底（100）形成第一沟槽。 第二沟槽（150）通过蚀刻半导体衬底（100）形成在第一沟槽的下部。 通过蚀刻氮化硅层图案形成凹陷的氮化硅层图案（122）。 通过蚀刻衬垫氧化物层图案形成凹陷衬垫氧化物层图案（112）。 通过对半导体衬底（100）执行退火处理，在有源区的上部和第二沟槽（150）的侧壁之间的边缘（300）被倒圆。

公开(公告)号：KR1020030079298A

公开(公告)日：2003-10-10

申请号：KR1020020018250

申请日：2002-04-03

Applicant: 삼성전자주식회사

Inventor： 유영섭 ,  박영욱 ,  임헌형 ,  황기현 ,  고창현 ,  이재동 ,  허형조

IPC: H01L27/04

Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to be capable of preventing junction leakage when forming a contact hole by uniformly forming a capping layer at the upper portion of a transition metal silicide layer. CONSTITUTION: A semiconductor device is provided with a semiconductor substrate(100) including a gate electrode(106) and a junction region(110) formed at both sides of the gate electrode, a transition metal silicide layer(115) selectively formed at the upper portion of the resultant structure, a capping layer(120) used as an etch stop layer, formed at the upper portion of the transition metal silicide layer, an interlayer dielectric(130) formed on the entire surface of the resultant structure, and a contact plug(140) formed in the interlayer dielectric and the capping layer for partially contacting the transition metal silicide layer.

Abstract translation: 目的：提供一种半导体器件及其制造方法，能够通过在过渡金属硅化物层的上部均匀形成覆盖层来防止形成接触孔时的结漏电。 构成：半导体器件设置有半导体衬底（100），该半导体衬底（100）包括栅电极（106）和形成在栅电极两侧的接合区（110），过渡金属硅化物层（115）选择性地形成在上部 所得结构的一部分，用作蚀刻停止层的覆盖层（120），形成在过渡金属硅化物层的上部，形成在所得结构的整个表面上的层间电介质（130）和接触 形成在层间电介质中的插塞（140）和用于部分地接触过渡金属硅化物层的覆盖层。

公开(公告)号：KR100396473B1

公开(公告)日：2003-09-02

申请号：KR1020010029753

申请日：2001-05-29

Applicant: 삼성전자주식회사

Inventor： 강만석 ,  허형조

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L21/28273 ,  Y10S438/978

Abstract: A semiconductor memory device having a floating gate and a method of manufacturing the same, where a conductive layer for a floating gate is deposited on a semiconductor substrate and etched to form a conductive layer pattern. An annealing of the semiconductor substrate is carried out in an ambient atmosphere of hydrogen gas. Alternatively, an entire surface of the conductive layer pattern is etched by a dry etching method or a wet etching method. As a result, at least one edge of the conductive layer pattern is rounded, which reduces the likelihood that an electric field is concentrated at the edge and reduces a likelihood that the dielectric layer formed on the floating gate is thinner at the edge.

Abstract translation: 一种具有浮栅的半导体存储器件及其制造方法，其中用于浮栅的导电层被沉积在半导体衬底上并被蚀刻以形成导电层图案。 半导体衬底的退火在氢气的环境气氛中进行。 或者，通过干蚀刻方法或湿蚀刻方法蚀刻导电层图案的整个表面。 结果，导电层图案的至少一个边缘变圆，这减少了电场集中在边缘的可能性，并降低了形成在浮置栅极上的介电层在边缘处更薄的可能性。

公开(公告)号：KR1020020090749A

公开(公告)日：2002-12-05

申请号：KR1020010029753

申请日：2001-05-29

Applicant: 삼성전자주식회사

Inventor： 강만석 ,  허형조

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L21/28273 ,  Y10S438/978

Abstract: PURPOSE: A semiconductor memory device having a floating gate and a manufacturing method thereof are provided to have a floating gate of which edge is round, and improve its endurance and data retention. CONSTITUTION: A field oxide layer(101) is formed on a semiconductor substrate to divide an active(102) and a field region. A tunnel oxide layer(104) is formed on the substrate. A conductive layer for floating gate is deposited on the tunnel oxide layer. By etching partially the conductive layer, a conductive pattern(106a) is formed. The edge(c) of the conductive pattern is rounded.

Abstract translation: 目的：提供一种具有浮动栅极的半导体存储器件及其制造方法，其具有边缘为圆形的浮动栅极，并提高其耐久性和数据保持性。 构成：在半导体衬底上形成场氧化物层（101）以分割活性（102）和场区域。 在衬底上形成隧道氧化物层（104）。 用于浮栅的导电层沉积在隧道氧化物层上。 通过部分地蚀刻导电层，形成导电图案（106a）。 导电图案的边缘（c）是圆形的。