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公开(公告)号：KR1020160009984A
公开(公告)日：2016-01-27
申请号：KR1020140090622
申请日：2014-07-17
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7848 , H01L21/76224 , H01L21/764 , H01L21/823412 , H01L21/823425 , H01L21/823481 , H01L21/823878 , H01L29/0847 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7812 , H01L29/7813
Abstract: 스트레서(stressor) 및절연패턴을갖는반도체소자에관한것이다. 기판상에활성영역을한정하는소자분리막이형성된다. 상기활성영역상에제1 게이트전극이형성된다. 상기소자분리막 상에제2 게이트전극이형성된다. 상기제1 게이트전극및 상기제2 게이트전극사이의상기활성영역내에트렌치가형성된다. 상기트렌치내에스트레서(stressor)가형성된다. 상기스트레서(stressor) 및상기소자분리막 사이에형성되고상기제2 게이트전극에인접한캐비티(cavity)가배치된다. 상기캐비티(cavity) 내에절연패턴이형성된다.
Abstract translation: 本发明涉及具有应力源和绝缘图案的半导体器件。 在衬底上形成用于限定有源区的器件隔离层。 在有源区上形成第一栅电极。 在器件隔离层上形成第二栅电极。 在第一栅电极和第二栅电极之间的有源区中形成沟槽。 应力源形成在沟槽中。 在应力器和器件隔离层之间形成空腔并与第二栅电极相邻。 绝缘图案形成在空腔中。
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Patent Agency Ranking
公开(公告)号：KR101515471B1
公开(公告)日：2015-05-06
申请号：KR1020080028510
申请日：2008-03-27
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242 , H01L21/205 , H01L21/316
Abstract: 고유전율을 가지는 지르코늄 산화막 형성 방법 및 이를 이용하는 반도체 장치의 형성 방법 및 이에 의해 형성되는 반도체 장치를 이용하는 시스템 장치를 제공한다. 유전율이 높은 지르코늄 산화막과 지르코늄 산질화막 2중 구조로 형성되거나, 지르코늄 산화막과 지르코늄 산질화막 및 지르코늄 산화막 3중 구조를 이용한 반도체 디바이스는 리키지가 없는 고유전막 구조로 넓은 면적의 전극막을 형성할 필요가 없어 단위 면적당 소자의 용량을 증가시킬 수 있다.
Abstract translation: 它提供了一种具有高介电常数和用于使用相同的系统中形成的半导体装置的形成方法的方法，以及使用由形成的半导体器件本装置的氧化锆膜。 或介电常数与高氧化锆和氮氧化锆双层结构，氧化锆和氧氮化锆层和氧化锆层3使用双结构的半导体器件形成的是没有必要的由一个唯一的导体膜结构以形成一个大面积的膜电极不是土地瑞奇 设备的单位面积容量可以增加。
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公开(公告)号：KR1020140092959A
公开(公告)日：2014-07-25
申请号：KR1020130001179
申请日：2013-01-04
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7848 , H01L21/823418 , H01L29/66545 , H01L29/66636
Abstract: A gate electrode is formed on an active region. An embedded stressor which fills a trench formed in the active layer is arranged. The active region has a sigma shape (∑-shape) which is formed by the trench. The embedded stressor includes a lower semiconductor layer and the upper semiconductor layer of the lower semiconductor layer. The upper end of the upper semiconductor layer protrudes from the upper end of the active region to be higher than the active region. The upper semiconductor layer is narrower than the lower semiconductor layer. The lateral surface of the upper semiconductor layer is dislocated from the lateral surface of the lower semiconductor layer.
Abstract translation: 栅电极形成在有源区上。 布置填充有源层中形成的沟槽的嵌入式应力器。 有源区具有由沟槽形成的σ形（Σ形）。 嵌入式应力器包括下半导体层和下半导体层的上半导体层。 上半导体层的上端从有源区的上端突出成高于有源区。 上半导体层比下半导体层窄。 上半导体层的侧表面从下半导体层的侧表面脱位。
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公开(公告)号：KR1020140038825A
公开(公告)日：2014-03-31
申请号：KR1020120105406
申请日：2012-09-21
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/7849 , H01L21/30604 , H01L21/76224 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L29/0649 , H01L29/161 , H01L29/165 , H01L29/42376 , H01L29/66477 , H01L29/66553 , H01L29/7848 , H01L29/6656 , H01L29/66636
Abstract: A method of manufacturing a semiconductor device is provided. A gate electrode is formed on a substrate. A first spacer, a second spacer, a third spacer are successively formed on the sidewall of the gate electrode. A recess region is formed by etching the substrate. A compressive stress pattern is formed in the recess region. A protection spacer is formed on the sidewall of the third spacer. When the recess region is formed, the lower part of the second spacer is removed to form a gap region between the first spacer and the third spacer. The protection spacer fills the gap region.
Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成栅电极。 第一间隔物，第二间隔物，第三间隔物依次形成在栅电极的侧壁上。 通过蚀刻衬底形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护间隔物。 当形成凹陷区域时，第二间隔件的下部被去除以在第一间隔件和第三间隔件之间形成间隙区域。 保护间隔物填充间隙区域。
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公开(公告)号：KR1020110009762A
公开(公告)日：2011-01-31
申请号：KR1020090067120
申请日：2009-07-23
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L29/76 , H01L21/823807 , H01L27/092 , H01L29/7843
Abstract: PURPOSE: An n type field effect MOS transistor and a manufacturing method thereof are provided to have high drain saturation current and increase the operation speed. CONSTITUTION: A gate structure is included on a substrate(100). The gate structure includes a gate oxide pattern and a gate electrode. A spacer(108) is included on the side wall of the gate structure. The n type impurity is injected under the surface of both sides of the gate structure.
Abstract translation: 目的：提供一种n型场效应MOS晶体管及其制造方法，以具有高的漏极饱和电流并提高操作速度。 构成：在衬底（100）上包括栅极结构。 栅极结构包括栅极氧化物图案和栅电极。 隔板（108）包括在栅极结构的侧壁上。 在栅极结构的两侧表面注入n型杂质。
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公开(公告)号：KR1020090097735A
公开(公告)日：2009-09-16
申请号：KR1020080023059
申请日：2008-03-12
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: C23C16/308 , C23C16/30 , C23C16/405 , C23C16/45529 , C23C16/45531 , C23C16/45542 , H01L21/3141 , H01L21/3145 , H01L21/31641 , H01L28/55
Abstract: A method for a zirconium carbon oxynitride insulation film, a semiconductor device using the same, and a manufacturing method thereof are provided to increase capacity of a device per unit area by excluding an electrode film of a wide dimension. A bottom electrode(180) is formed on a semiconductor substrate(100). A zirconium organic nitrogen source is absorbed on the bottom electrode. A non-reactive source is removed from the zirconium organic nitrogen. A zirconium carbon oxynitride layer is formed by supplying an oxidizer gas to the zirconium organic nitrogen absorption layer. The non-reactive oxidizer is removed. A nitriding agent is supplied to the zirconium carbon oxynitride layer. A top electrode(195) is formed on the zirconium carbon oxynitride layer.
Abstract translation: 提供锆碳氧氮化物绝缘膜的方法，使用该方法的半导体器件及其制造方法，通过排除宽尺寸的电极膜来增加每单位面积的器件的容量。 底部电极（180）形成在半导体衬底（100）上。 锆有机氮源被吸收在底部电极上。 从有机氮中除去非反应性源。 通过向锆有机氮吸收层供给氧化剂气体来形成碳氮氧化锆锆层。 去除非反应性氧化剂。 向氮氧化锆层供给氮化剂。 在氮氧化锆锆层上形成顶部电极（195）。
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