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公开(公告)号：KR1019990000027A
公开(公告)日：1999-01-15
申请号：KR1019970022651
申请日：1997-06-02
Applicant: 삼성전자주식회사
Inventor： 신유철
IPC: H01L27/06
Abstract: 반도체 장치의 커패시터 및 그 제조 방법을 개시한다. 본 발명은 반도체 기판 상에 형성되고, 불순물이 도핑(doping)된 폴리 실리콘막(polysilicon layer)막을 이용한 하부 전극과 그 측벽에 형성된 질화 티타늄(TiN)막을 이용한 금속 스페이서(metal spacer)를 포함한다. 이때, 하부 전극으로 실린더형 전극(cylinder type node) 또는 스택형 전극(stack type node)을 이용한다. 금속 스페이서 및 하부 전극을 뒤덮는 산화 탄탈늄(Ta
2 O
5 )막을 이용한 유전막 패턴과 유전막 패턴을 뒤덮는 상부 전극을 포함한다. 이때 상부 전극으로 불순물이 도핑된 폴리 실리콘막과 질화 티타늄막의 이중막을 이용한다.-
公开(公告)号：KR1020150122369A
公开(公告)日：2015-11-02
申请号：KR1020140048124
申请日：2014-04-22
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/11514 , H01L27/11509
Abstract: 본발명은반도체장치를제공한다. 이장치에서는셀 어레이회로부아래에이를구동시키는주변회로부가배치된다. 또한주변회로부와연결되는제 1 도전라인들과상기셀 어레이회로부를연결하는제 2 도전라인들이연결영역상에서같은형태를가지며서로중첩된다.
Abstract translation: 本发明提供一种半导体器件。 用于操作单元阵列电路单元的周围电路单元布置在器件中的单元阵列电路单元的下方。 此外，连接到周围电路单元的第一导线和用于连接电池阵列电路单元的第二导线在连接区域上以相同的形状彼此重叠。
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公开(公告)号：KR1020150042358A
公开(公告)日：2015-04-21
申请号：KR1020130120720
申请日：2013-10-10
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11582 , H01L21/76802 , H01L27/1157 , H01L27/11575 , H01L21/76877 , H01L21/823487 , H01L27/2436 , H01L27/2463 , H01L29/7926
Abstract: 반도체장치및 그제조방법이제공된다. 반도체장치는제1 기판상의주변회로구조체, 상기주변회로구조체상의셀 어레이구조체, 및상기주변회로구조체및 상기셀 어레이구조체사이의제2 기판을포함한다. 상기셀 어레이구조체는상기제2 기판상에적층된복수개의게이트전극들을포함하는적층구조체, 및상기적층구조체및 상기제2 기판을관통하는관통홀 내에형성되고상기주변회로구조체에접하는수직반도체패턴을포함한다.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括在第一衬底上的周围电路结构，围绕电路结构的电池阵列结构，以及在周围电路结构和电池阵列结构之间的第二衬底。 电池阵列结构包括层叠结构，其包括设置在第二基板上的多个栅极电极和垂直半导体图案，该垂直半导体图案形成在穿透层叠结构和第二基板的穿透孔中，并且邻近周围电路 结构体。
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公开(公告)号：KR1020060134757A
公开(公告)日：2006-12-28
申请号：KR1020050054687
申请日：2005-06-23
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/115 , H01L27/11521 , H01L21/28141 , H01L21/28273 , H01L27/11526
Abstract: A non-volatile memory device having a fin-type active region is provided to prevent an interconnection layer connected to a source/drain region from being connected to a lower sidewall of an active region by forming a sidewall passivation layer on the sidewall of a pin-type active region in which the source/drain region is formed. An isolation layer is formed in a semiconductor substrate. A pin-type active region(12) is formed between the isolation layers. A wordline(WLn) has a surface confronting the sidewall of the active region, passing through a portion over the active region. A source/drain region(21s,21d) is formed in the active region. An interlayer dielectric comes in contact with the upper surface of the active region. A sidewall passivation layer comes in contact with the sidewall of the active region in which the source/drain region is formed. The sidewall passivation layer is an insulation layer having etch selectivity with respect to the interlayer dielectric. The interlayer dielectric includes an etch blocking layer which comes in contact with the upper surface of the active region and has etch selectivity with respect to the isolation layer. The sidewall passivation layer is an isolation layer in contact with the etch blocking layer.
Abstract translation: 提供具有鳍型有源区的非易失性存储器件，以通过在引脚的侧壁上形成侧壁钝化层来防止连接到源/漏区的互连层与有源区的下侧壁连接 型有源区，其中形成源极/漏极区。 在半导体衬底中形成隔离层。 在隔离层之间形成引脚型有源区（12）。 字线（WLn）具有面对有源区的侧壁的表面，穿过有源区上的部分。 源极/漏极区域（21s，21d）形成在有源区域中。 层间电介质与有源区的上表面接触。 侧壁钝化层与其中形成源极/漏极区的有源区的侧壁接触。 侧壁钝化层是相对于层间电介质具有蚀刻选择性的绝缘层。 层间电介质包括蚀刻阻挡层，其与有源区的上表面接触并且具有相对于隔离层的蚀刻选择性。 侧壁钝化层是与蚀刻阻挡层接触的隔离层。
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Patent Agency Ranking
公开(公告)号：KR1020060110755A
公开(公告)日：2006-10-25
申请号：KR1020060027595
申请日：2006-03-27
Applicant: 삼성전자주식회사
IPC: G11C16/28 , H01L27/115
CPC classification number: G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
Abstract: A NAND flash memory device having a dummy memory cell is provided to improve program and erase characteristics of a memory cell, by making a dummy word line into a floating state during erase operation or programming of the dummy memory cell before or after erasing memory cells. Plural memory cells(MC14,MC15) are connected in series. One or more dummy memory cell(DC1) is connected to the memory cells in series. A selection transistor(ST2) is connected to the dummy memory cell. A control circuit(510) applies a first word line voltage to unselected memory cells, and applies a second word line voltage higher than the first word line voltage to a selected memory cell, and applies a third word line voltage lower than the first word line voltage to the dummy memory cell, during program operation.
Abstract translation: 提供具有虚拟存储单元的NAND闪存器件，用于通过在擦除存储器单元之前或之后的擦除操作或伪存储器单元的编程期间将虚拟字线置为浮置状态来改善存储器单元的编程和擦除特性。 多个存储单元（MC14，MC15）串联连接。 一个或多个虚拟存储器单元（DC1）串联连接到存储器单元。 选择晶体管（ST2）连接到虚拟存储单元。 控制电路（510）将第一字线电压施加到未选择的存储单元，并将比第一字线电压高的第二字线电压施加到所选存储单元，并施加低于第一字线电压的第三字线电压 在程序运行期间，向虚拟存储单元提供电压。
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公开(公告)号：KR1020050076114A
公开(公告)日：2005-07-26
申请号：KR1020040003926
申请日：2004-01-19
Applicant: 삼성전자주식회사
Inventor： 신유철
IPC: G11C29/00
CPC classification number: G11C29/04 , G11C5/025 , G11C7/18 , G11C16/0483
Abstract: 어드레스 식별표시를 갖는 반도체 기억소자를 제공한다. 이 소자는 반도체 기판에 형성된 복수개의 라인형 패턴과, 상기 라인형 패턴들의 단부들이 사선으로 배열된 복수개의 데이타 블록을 포함한다. 인접한 데이타 블록의 라인형 패턴들이 서로 대칭적으로 배열되어 상기 라인형 패턴들의 단부들 사이에 더미 영역이 정의된다. 상기 더미 영역에 형성된 더미 패턴을 포함한다. 본 발명에서 상기 더미 패턴은 데이타 블록을 식별할 수 있는 식별표시가 되어 있다. 예컨대, 상기 식별표시는 대응되는 데이타 블록 쌍을 식별하는 서수일 수 있다.
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公开(公告)号：KR100414211B1
公开(公告)日：2004-01-07
申请号：KR1020010013930
申请日：2001-03-17
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11529 , H01L29/792
Abstract: A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure and a fabrication method thereof are provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can be also thinner than the equivalent thickness of the cell gate insulation layer.
Abstract translation: 提供了具有MONOS（金属氧化物 - 氮化物 - 氧化物 - 半导体）栅极结构的非易失性存储器件及其制造方法。 该器件包括选择晶体管和单元晶体管，单元晶体管包括形成在单元阵列区域中的单元栅极绝缘层和具有低压栅极绝缘层的低压MOS晶体管和具有高压栅极的高压MOS晶体管 绝缘层形成在外围电路区域中。 低压栅极绝缘层比高压栅极绝缘层更薄。 低压栅极绝缘层也可以比单元栅极绝缘层的等效厚度薄。
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公开(公告)号：KR1020030090368A
公开(公告)日：2003-11-28
申请号：KR1020020028647
申请日：2002-05-23
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954
Abstract: PURPOSE: A NAND-type non-volatile memory device with a SONOS gate structure and a fabricating method therefor are provided to increase a drain current by making a string select gate insulation layer and a ground select gate insulation layer formed of a single layered structure or a double layered structure, and to prevent a leakage current by making a blocking insulation layer composed of a high dielectric material. CONSTITUTION: A field oxide layer(32) for defining an active region is formed on a semiconductor substrate(31). A string select line(41s) and a ground select line(41g) are parallel with each other, crossing the upper portion of the active region. A plurality of word lines cross the upper portion of the active region, interposed between the string select line and the ground select line. A cell gate insulation layer(38w) in which a tunnel insulation layer(33), a charge trapping layer(35) and a blocking insulation layer(37) are sequentially stacked is interposed between each word line and the active region. The string select gate insulation layer(38s) is interposed between the string select line and the active region. The ground select gate insulation layer(38g) is interposed between the ground select line and the active region. The string select gate insulation layer and the ground select gate insulation layer are formed of a single layered structure composed of a blocking insulation layer or a double layered structure composed of the tunnel insulation layer and the blocking insulation layer.
Abstract translation: 目的：提供具有SONOS栅极结构的NAND型非易失性存储器件及其制造方法，以通过使串选择栅极绝缘层和由单层结构形成的接地选择栅绝缘层来增加漏极电流， 双层结构，并且通过制造由高介电材料构成的阻挡绝缘层来防止漏电流。 构成：在半导体衬底（31）上形成用于限定有源区的场氧化物层（32）。 串选择线（41s）和接地选择线（41g）彼此平行，与有源区域的上部交叉。 多个字线横跨有源区域的上部，插入在串选择线和地选线之间。 其中隧道绝缘层（33），电荷俘获层（35）和隔离绝缘层（37）顺序堆叠的单电池栅极绝缘层（38w）插入在每个字线和有源区域之间。 串选择栅极绝缘层（38s）插入在串选择线和有源区之间。 接地选择栅绝缘层（38g）介于接地选择线和有源区之间。 串选择栅极绝缘层和接地选择栅极绝缘层由由隔离绝缘层或由隧道绝缘层和阻挡绝缘层构成的双层结构构成的单层结构形成。
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公开(公告)号：KR100399363B1
公开(公告)日：2003-09-26
申请号：KR1020010001613
申请日：2001-01-11
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L27/11521 , H01L27/115
Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.
Abstract translation: 一种半导体器件，包括多条由线形组成的栅极线，用作多个晶体管中的栅电极，并且通过栅绝缘层与衬底分离，每个栅绝缘层具有上金属硅化物层; 以及仅通过执行杂质注入工艺而在所述栅极线之间的衬底上形成的多个源极/漏极区域。
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