公开(公告)号：KR100400044B1

公开(公告)日：2003-09-29

申请号：KR1020010042822

申请日：2001-07-16

Applicant: 삼성전자주식회사

Inventor： 박종철 ,  김동현 ,  권오익 ,  조혜진

IPC: H01L21/3065

CPC classification number: C23C16/45565 ,  C23C16/45589 ,  H01L21/67017

Abstract: A shower head comprises a top plate (10) having a gas port (12), a face plate (20), a first baffle plate (30), a second baffle plate (40) and a gap controller. A shower head for supplying a reactant gas to a process region within a reaction chamber during manufacture of a semiconductor device, comprises: (i) a top plate having a gas port for introducing the reactant gas supplied from an outside source to the reaction chamber; (ii) a face plate disposed opposite the process region, and having through holes; (iii) a first baffle plate having through holes, and disposed between the top plate and the face plate so that it is capable of moving up or down, and has a top surface that defines a first gap (70) for forming a first lateral flow passage of the reactant gas; (iv) a second baffle plate having through holes, and disposed between the first baffle and the face plate so that it is capable of moving up or down, and has a top surface that defines a second gap for forming a second lateral flow passage of the reactant gas between the first and second baffle plates; and (v) a gap controller for determining a width of the first gap and a width of the second gap.

Abstract translation: 一种淋浴喷头，包括具有气口（12），面板（20），第一挡板（30），第二挡板（40）和间隙控制器的顶板（10）。 一种用于在制造半导体器件时向反应室内的处理区域供应反应气体的喷头，包括：（i）具有气体端口的顶板，用于将从外部源供应的反应气体引入反应室; （ii）与处理区域相对设置并具有通孔的面板; （iii）具有通孔的第一挡板，所述第一挡板设置在所述顶板和所述面板之间以使其能够向上或向下移动，并且具有限定第一间隙（70）的顶表面，所述第一间隙（70）用于形成第一横向 反应气体的流动通道; （iv）具有通孔的第二挡板，所述第二挡板设置在所述第一挡板和所述面板之间以能够向上或向下移动，并且具有限定用于形成第二侧向流动通道的第二间隙的顶表面， 第一和第二挡板之间的反应气体; 和（v）间隙控制器，用于确定第一间隙的宽度和第二间隙的宽度。

公开(公告)号：KR1020030038865A

公开(公告)日：2003-05-17

申请号：KR1020010069010

申请日：2001-11-06

Applicant: 삼성전자주식회사

Inventor： 조혜진 ,  김동현 ,  박종철

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a self-alignment contact hole of a semiconductor device is provided to prevent a bit line from being contacted with conductive material by conserving the original thickness of a nitride silicon layer. CONSTITUTION: After sequentially forming a conductive layer and the first isolating layer made of a nitride silicon layer on a semiconductor substrate(30), a photoresist layer pattern is formed on the resultant structure. An isolating layer pattern(40) is formed by etching the first isolating layer using the photoresist pattern as a mask. At this time, the conductive layer is partially etched at the range of 40-60%. After removing the photoresist layer pattern, a conductive layer pattern made of a titanium nitride layer pattern(42) and a tungsten layer pattern(44), is formed by etching the conductive layer using the isolating layer pattern(40) as a mask. At this time, the original thickness of the isolating layer pattern(40) is conserved because of the pre-etching of the conductive layer. After an insulating spacer(46) is formed at both sidewalls of the isolating and conductive layer pattern, the second isolating layer(48) is formed on the entire surface of the resultant structure. A self-alignment contact hole(50) is formed in the resultant structure for exposing the isolating layer pattern(40).

Abstract translation: 目的：提供一种用于形成半导体器件的自对准接触孔的方法，以通过保留氮化硅层的原始厚度来防止位线与导电材料接触。 构成：在半导体衬底（30）上依次形成导电层和由氮化物硅层制成的第一隔离层之后，在所得结构上形成光刻胶层图案。 通过使用光致抗蚀剂图案作为掩模蚀刻第一隔离层来形成隔离层图案（40）。 此时，导电层被部分地蚀刻在40-60％的范围内。 在去除光致抗蚀剂层图案之后，通过使用隔离层图案（40）作为掩模蚀刻导电层，形成由氮化钛层图案（42）和钨层图案（44）制成的导电层图案。 此时，由于导电层的预蚀刻，隔离层图案（40）的原始厚度是保守的。 在绝缘间隔物（46）形成在隔离导电层图案的两个侧壁处，第二隔离层（48）形成在所得结构的整个表面上。 在所得结构中形成自对准接触孔（50），用于暴露隔离层图案（40）。

公开(公告)号：KR101826217B1

公开(公告)日：2018-03-23

申请号：KR1020170094427

申请日：2017-07-25

Applicant: 삼성전자주식회사

Inventor： 이창현 ,  손병근 ,  조혜진

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/06 ,  H01L21/768 ,  H01L21/8234

Abstract: 3차원반도체기억소자및 그제조방법을제공한다. 이소자에따르면, 기판의웰 영역내에공통소오스영역이배치될수 있으며, 공통소오스영역상에적층된게이트패턴들을포함하는적층-구조체가배치될수 있다. 수직형활성패턴들이적층-구조체를관통할수 있다. 수직형활성패턴은그 아래의기판내에형성된리세스영역으로인하여공통소오스영역을관통하는전기적통로(electrical path)를경유하여웰 영역과연결될수 있다.

公开(公告)号：KR1020080085955A

公开(公告)日：2008-09-25

申请号：KR1020070027417

申请日：2007-03-21

Applicant: 삼성전자주식회사

Inventor： 강희수 ,  조혜진 ,  이충호 ,  박규찬

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/28282

Abstract: A non-volatile memory device is provided to minimize a distance between a first covalence cell gate electrode and a ground selection gate electrode and a distance between a second covalence cell gate electrode and a string selection gate electrode, operation failure of the first and second covalence cell gate electrodes, and to improve integration degree of a semiconductor device. A non-volatile memory device includes cell gate electrodes(104), a ground selection gate electrode(108), a string selection gate electrode, and a well region(102). The cell gate electrodes are disposed on a semiconductor substrate parallel with each other at a first interval. The ground selection gate electrode is spaced a first interval apart from a first covalence cell gate electrode among the cell gate electrodes. The string selection gate electrode is spaced a first interval apart from a second covalence cell gate electrode among the cell gate electrodes. The well region is formed on a substrate under the cell gate electrodes, the ground selection gate electrode, and the string selection gate electrode and a substrate between the respectively gate electrodes in which the same impurities are continuously doped.

Abstract translation: 提供非易失性存储器件以最小化第一共用单元栅电极和接地选择栅电极之间的距离以及第二共价单元栅电极和串选择栅电极之间的距离，第一和第二共价的操作失败 单元栅电极，并提高半导体器件的集成度。 非易失性存储器件包括单元栅电极（104），接地选择栅电极（108），串选择栅电极和阱区（102）。 电池栅电极以第一间隔彼此平行地设置在半导体衬底上。 接地选择栅电极与单元栅电极之间的第一共价单元栅电极隔开第一间隔。 串选择栅电极与单元栅电极之间的第二共价单元栅电极隔开第一间隔。 在单元栅电极，接地选择栅电极和串选择栅电极之下的衬底上形成阱区，并且在连续掺杂相同杂质的各个栅电极之间形成衬底。

公开(公告)号：KR1020050019468A

公开(公告)日：2005-03-03

申请号：KR1020030057263

申请日：2003-08-19

Applicant: 삼성전자주식회사

Inventor： 김성민 ,  박동건 ,  이성영 ,  최정동 ,  이신애 ,  윤은정 ,  조혜진

IPC: H01L21/335

Abstract: PURPOSE: A structure of a vertical transistor and a method for forming the same are provided to control the channel length without relying upon a photolithography. CONSTITUTION: A first cylindrical semiconductor pillar(101a) is formed on a semiconductor substrate. A second cylindrical semiconductor pillar(101p) placed in the center of the first semiconductor pillar has higher height and less diameter than the first semiconductor pillar. A gate dielectric(103) is formed on the top of the first semiconductor pillar and around the second semiconductor pillar. A cylindrical gate electrode(105) having the same diameter as the first semiconductor pillar is formed on the top of the first semiconductor pillar and around the second semiconductor pillar. A first cylindrical dielectric film(109) having the same diameter as the gate electrode is formed on the top of the gate electrode and around of the second semiconductor pillar. A silicon oxide film(111) surrounds the first semiconductor pillar, the gate electrode and the first dielectric film.

Abstract translation: 目的：提供垂直晶体管的结构及其形成方法来控制沟道长度而不依赖于光刻。 构成：在半导体衬底上形成第一圆柱形半导体柱（101a）。 放置在第一半导体柱的中心的第二圆柱形半导体柱（101p）具有比第一半导体柱更高的高度和更小的直径。 栅电介质（103）形成在第一半导体柱的顶部上并且围绕第二半导体柱。 在第一半导体柱的顶部和第二半导体柱的周围形成具有与第一半导体柱相同直径的圆柱形栅电极（105）。 在栅电极的顶部和第二半导体柱的周围形成具有与栅电极相同直径的第一圆柱形电介质膜（109）。 氧化硅膜（111）包围第一半导体柱，栅电极和第一绝缘膜。

公开(公告)号：KR1020050015975A

公开(公告)日：2005-02-21

申请号：KR1020040034025

申请日：2004-05-13

Applicant: 삼성전자주식회사

Inventor： 김성민 ,  김동원 ,  윤은정 ,  박동건 ,  이성영 ,  최정동 ,  이신애 ,  조혜진

IPC: H01L21/8232 ,  B82Y10/00

Abstract: PURPOSE: A metal oxide semiconductor transistor having three-dimensional channels and a fabricating method thereof are provided to prevent reduction of a contact area between source and drain regions by forming a trench within a semiconductor substrate. CONSTITUTION: An active region is projected from a predetermined region of a semiconductor substrate. An isolation layer(21A) is used for surrounding the active region and has a surface lower than an upper surface of the active region. At least one center trench is used for defining a plurality of channel regions recessed from a center part of the active region and a source/drain region for connecting both ends of the channel regions to each other. A gate electrode(25A) is used for covering sidewalls and upper surfaces of the channel regions across upper parts of the channel regions.

Abstract translation: 目的：提供具有三维通道的金属氧化物半导体晶体管及其制造方法，以通过在半导体衬底内形成沟槽来防止源极和漏极区域之间的接触面积减小。 构成：从半导体衬底的预定区域突出有源区域。 隔离层（21A）用于围绕有源区域并且具有比有源区域的上表面低的表面。 使用至少一个中心沟槽来限定从有源区域的中心部分凹陷的多个沟道区域和用于将沟道区域的两端彼此连接的源极/漏极区域。 栅极电极（25A）用于覆盖沟道区域的侧壁和上表面，跨过沟道区域的上部。

公开(公告)号：KR1020030008068A

公开(公告)日：2003-01-24

申请号：KR1020010042822

申请日：2001-07-16

Applicant: 삼성전자주식회사

Inventor： 박종철 ,  김동현 ,  권오익 ,  조혜진

IPC: H01L21/3065

CPC classification number: C23C16/45565 ,  C23C16/45589 ,  H01L21/67017

Abstract: PURPOSE: A shower head of a wafer processing apparatus having an interval control device is provided to control the amount of reaction gas by installing the interval control device between two baffle plates. CONSTITUTION: A top plate(10) has a gas inflow hole(12) for transferring a reaction gas into a process chamber. A face plate(20) faces a process region of the process chamber. A plurality of through-holes are formed in the face plate(20). The first baffle plate(30) and the second baffle plate(40) are installed between the top plate(10) and the face plate(20). An interval control device is formed on an upper face of the first baffle plate(30). The interval control device is formed with the first spacer ring(92). An interval control device including the second spacer ring(94) is formed between the first and the second baffle plate(30,40). The positions of the first and the second baffle plate(30,40) are determined by controlling thickness of the first and the second ring(92,94). A guide baffle plate(50) is installed on the first baffle plate(30).

Abstract translation: 目的：提供具有间隔控制装置的晶片处理装置的喷头，以通过在两个挡板之间安装间隔控制装置来控制反应气体的量。 构成：顶板（10）具有用于将反应气体输送到处理室中的气体流入孔（12）。 面板（20）面向处理室的处理区域。 多个通孔形成在面板（20）中。 第一挡板（30）和第二挡板（40）安装在顶板（10）和面板（20）之间。 间隔控制装置形成在第一挡板（30）的上表面上。 间隔控制装置形成有第一间隔环（92）。 包括第二隔离环（94）的间隔控制装置形成在第一和第二挡板（30,40）之间。 通过控制第一和第二环（92,94）的厚度来确定第一和第二挡板（30,40）的位置。 引导挡板（50）安装在第一挡板（30）上。

公开(公告)号：KR1020170090387A

公开(公告)日：2017-08-07

申请号：KR1020170094427

申请日：2017-07-25

Applicant: 삼성전자주식회사

Inventor： 이창현 ,  손병근 ,  조혜진

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/06 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L27/11582 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/7926

Abstract: 3차원반도체기억소자및 그제조방법을제공한다. 이소자에따르면, 기판의웰 영역내에공통소오스영역이배치될수 있으며, 공통소오스영역상에적층된게이트패턴들을포함하는적층-구조체가배치될수 있다. 수직형활성패턴들이적층-구조체를관통할수 있다. 수직형활성패턴은그 아래의기판내에형성된리세스영역으로인하여공통소오스영역을관통하는전기적통로(electrical path)를경유하여웰 영역과연결될수 있다.

Abstract translation: 提供了一种三维半导体存储器件及其制造方法。 根据本发明，可以在衬底的阱区中布置公共源极区，并且可以布置包括堆叠在公共源极区上的栅极图案的堆叠结构。 垂直活动图案可以穿透堆叠结构。 由于在下面的衬底中形成的凹陷区域，垂直有源图案可以经由通过公共源极区域的电路径连接到阱区域。

公开(公告)号：KR101763420B1

公开(公告)日：2017-08-01

申请号：KR1020100091140

申请日：2010-09-16

Applicant: 삼성전자주식회사

Inventor： 이창현 ,  손병근 ,  조혜진

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

Abstract: 3차원반도체기억소자및 그제조방법을제공한다. 이소자에따르면, 기판의웰 영역내에공통소오스영역이배치될수 있으며, 공통소오스영역상에적층된게이트패턴들을포함하는적층-구조체가배치될수 있다. 수직형활성패턴들이적층-구조체를관통할수 있다. 수직형활성패턴은그 아래의기판내에형성된리세스영역으로인하여공통소오스영역을관통하는전기적통로(electrical path)를경유하여웰 영역과연결될수 있다.

公开(公告)号：KR101408743B1

公开(公告)日：2014-06-18

申请号：KR1020070128353

申请日：2007-12-11

Applicant: 삼성전자주식회사

Inventor： 강희수 ,  이충호 ,  조혜진

IPC: H01L23/12

CPC classification number: H01L23/34 ,  H01L21/823412 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7842 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 반도체 패키지는 반도체 칩, 지지기판 및 몰딩 부재를 포함한다. 반도체 칩은 반도체 기판 및 반도체 기판 상에 제1 방향으로 배열된 복수의 셀 트랜지스터들을 포함한다. 지지기판은 상면에 반도체 칩을 고정하며, 온도가 상승함에 따라 휘어져 제1 방향으로 반도체 칩에 인장 응력을 가한다. 제1 방향과 동일한 방향을 따라 지지기판은 상방으로 휘어지거나, 제1 방향과 수직한 제2 방향을 따라 지지기판은 하방으로 휘어질 수 있다. 몰딩 부재는 반도체 칩 및 지지기판을 감싼다.