公开(公告)号：KR1019990008794A

公开(公告)日：1999-02-05

申请号：KR1019970030926

申请日：1997-07-04

Applicant: 삼성전자주식회사

Inventor： 한지훈

IPC: G06K9/20

Abstract: 본 발명은 원고로부터 데이터 독취를 수행하는 독취부와, 독취된 데이터를 이진화(binarization)하는 처리부와, 상기 처리부에 의해 독취 데이터를 처리하는 과정에 생성되는 인접한 오류 화소 정보를 슬라이스 단위로 저장하는 메모리와, 상기 독취부의 왕복 운동을 위한 모터 구동부와, 상기 독취부가 좌에서 우로 이동하며 슬라이스 단위로 독취할 때 증가 카운팅하는 증가 카운터와, 상기 독취부가 우에서 좌로 이동하며 슬라이스 단위로 독취할 때 감소 카운팅하는 감소 카운터와, 독취할 원고를 이송하는 원고 이송부와, 상기 독취부의 독취 방향을 나타내는 독취 방향 플레그 레지스터를 포함하는 셔틀 방식의 양방향 원고 독취 장치로 양방향 독취를 가능하게 한다.
본 발명에 따르면 독취부를 좌에서 우로 이동하게 하면서 독취 작업을 수행하고 다음 밴드를 독취할 때는 우에서 좌로 이동하면서 원고 독취를 수행하여 기존 방식에 비해 두 배의 빠른 원고 독취를 가능하게 하는 효과가 있다.

公开(公告)号：KR101692364B1

公开(公告)日：2017-01-05

申请号：KR1020100113349

申请日：2010-11-15

Applicant: 삼성전자주식회사

Inventor： 나종훈 ,  박영우 ,  곽동화 ,  김태용 ,  한지훈 ,  유장현 ,  이동식 ,  박수진

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/0207 ,  H01L21/28273 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11524

Abstract: 비휘발성메모리장치의제조방법및 그에의해제조된비휘발성메모리장치가제공된다. 본발명의일 실시예에따른비휘발성메모리장치의제조방법은, 복수의트렌치에의해활성영역이정의된기판을제공하고, 복수의트렌치를포함하는기판상에제1 소자분리막을형성하고, 제1 소자분리막상에희생층을형성하여트렌치를매립하되, 희생층은트렌치의하부영역을매립하는제1 영역과, 하부영역이외의영역을매립하는제2 영역을포함하고, 희생층의제2 영역을제거하고, 제1 소자분리막및 희생층의제1 영역상에제2 소자분리막을형성하고, 희생층의제1 영역을제거하여트렌치내에에어갭을형성하고, 에어갭을유지하며제1 소자분리막의일부및 제2 소자분리막의일부를제거하는것을포함한다.

Abstract translation: 一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽， 所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域 牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

公开(公告)号：KR1020150129242A

公开(公告)日：2015-11-19

申请号：KR1020140055685

申请日：2014-05-09

Applicant: 삼성전자주식회사

Inventor： 성호준 ,  심재황 ,  한지훈

IPC: H01L21/027 ,  G03F7/20

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L21/0274 ,  H01L2924/00

Abstract: 본발명은반도체장치의제조방법및 이에의해제조된반도체장치를제공한다. 이방법에서는넓은폭을가지는패턴들을형성하기위한포토레지스트패턴이, 워드라인의폭(1F)에해당되는두께의세배이상의간격의제 1 스페이서패턴을형성한후에형성된다.

Abstract translation: 本发明涉及半导体器件的制造方法及其制造的半导体器件。 在该方法中，形成具有宽于字线宽度（1F）的三倍以上的间隔的第一间隔图案，形成用于形成宽度宽的图案的光致抗蚀剂图案。

公开(公告)号：KR1020140110388A

公开(公告)日：2014-09-17

申请号：KR1020130024622

申请日：2013-03-07

Applicant: 삼성전자주식회사

Inventor： 유장현 ,  박형 ,  박봉태 ,  한지훈

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L21/28141 ,  H01L21/28273 ,  H01L21/31144 ,  H01L21/3213 ,  H01L2924/00

Abstract: The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device manufactured by the same. The method is to form the patterns of a fine pitch which overcomes the limit of an exposure process through a photolithography process and two spacer processes. Also, a line part and a pad part are simultaneously defined by the one-time photolithography process, thereby having no need to perform a separate photolithography process for forming the pad part only. Therefore, mask misalignment or bridge problems can be solved.

Abstract translation: 本发明涉及一种制造半导体器件的方法及其制造的半导体器件。 该方法是形成精细间距的图案，其克服了通过光刻工艺和两个间隔物工艺的曝光过程的极限。 此外，通过一次光刻工艺同时限定线部分和焊盘部分，从而不需要仅进行用于形成焊盘部分的单独的光刻工艺。 因此，可以解决掩模未对准或桥接问题。

公开(公告)号：KR1020120091621A

公开(公告)日：2012-08-20

申请号：KR1020110011497

申请日：2011-02-09

Applicant: 삼성전자주식회사

Inventor： 이동식 ,  유장현 ,  한지훈 ,  박영우 ,  허성회 ,  주상익

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764 ,  H01L27/11556 ,  H01L27/11582

Abstract: PURPOSE: A method for manufacturing a nonvolatile memory device is provided to remove an air gap filling process in a part of an area by selectively forming an air gap in a first area. CONSTITUTION: A substrate with a first region and a second region is provided. A first dielectric layer(120) and a charge storage floating pattern(130) are successively laminated on the substrate. A plurality of trenches(105) is filled with first insulation materials. A first recess is formed in the first area by removing the first insulation materials of the first area. A second insulation material(160) is formed on the upper side of the first recess. An air gap(110) is formed on the lower side of the first recess by removing sacrificial materials.

Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，以通过在第一区域中选择性地形成气隙来去除区域的一部分中的气隙填充过程。 构成：提供具有第一区域和第二区域的衬底。 第一电介质层（120）和电荷存储浮置图案（130）依次层叠在基板上。 多个沟槽（105）填充有第一绝缘材料。 通过去除第一区域的第一绝缘材料，在第一区域中形成第一凹部。 第二绝缘材料（160）形成在第一凹部的上侧。 通过去除牺牲材料，在第一凹部的下侧形成气隙（110）。

公开(公告)号：KR1020120019208A

公开(公告)日：2012-03-06

申请号：KR1020100082475

申请日：2010-08-25

Applicant: 삼성전자주식회사

Inventor： 이종민 ,  박재관 ,  한지훈

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/42324 ,  H01L29/4234 ,  H01L21/31051 ,  H01L21/76224

Abstract: PURPOSE: A method for manufacturing a nonvolatile memory device is provided to reduce the resistance of a word line by widely forming an area of a second metal silicide pattern. CONSTITUTION: A stack gate structure(10) including a lower structure(200) and a first poly silicon pattern is formed on a substrate. The lower structure includes a first dielectric film pattern(210), a charge storage film pattern(220), and a second dielectric film pattern(230). An insulation layer(130) covers the stack gate structure. A trench is formed on the insulation layer by partially removing the first poly silicon pattern. A metal film pattern is formed in the trench to be located on the first poly silicon pattern.

Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，通过广泛地形成第二金属硅化物图案的区域来减小字线的电阻。 构成：在基板上形成包括下部结构（200）和第一多晶硅图案的堆叠栅极结构（10）。 下部结构包括第一电介质膜图案（210），电荷存储膜图案（220）和第二电介质膜图案（230）。 绝缘层（130）覆盖堆叠栅极结构。 通过部分去除第一多晶硅图案，在绝缘层上形成沟槽。 在沟槽中形成金属膜图案以位于第一多晶硅图案上。

公开(公告)号：KR1020090065207A

公开(公告)日：2009-06-22

申请号：KR1020070132683

申请日：2007-12-17

Applicant: 삼성전자주식회사

Inventor： 황병준 ,  박재관 ,  한지훈 ,  진소위 ,  임남수

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L27/10891 ,  H01L27/2463

Abstract: A NAND flash memory device having a contact for controlling electric potential of a well is provided to maintain an electrically dependent state of a second well part of active regions without removing an unnecessary part by a trimming process. A plurality of active areas having a line shape is extended in a first direction on a substrate. A first well of a first conductive type is formed on the active areas. A plurality of word lines(120) are extended in a second direction perpendicular to the first direction on the first well in order to cross the active regions in order to form a plurality of memory cells. A pair of dummy word lines are maintained in a bias voltage state of 0V. A contact for applying a bias is formed between a first dummy word line(140A) and a second dummy word line(140B) in the partial active region which is selected from the active regions. The contact is formed to apply a well bias voltage to the first well.

Abstract translation: 提供具有用于控制阱的电位的触点的NAND快闪存储器件，以保持活性区域的第二阱部分的电依赖状态，而不需要通过修整过程去除不需要的部分。 具有线状的多个有源区域在基板上沿第一方向延伸。 第一导电类型的第一阱形成在有源区上。 多个字线（120）在垂直于第一阱上的第一方向的第二方向上延伸以跨过有源区域以形成多个存储单元。 一对虚拟字线保持在0V的偏置电压状态。 在从有源区域中选择的部分有源区域中的第一虚拟字线（140A）和第二虚拟字线（140B）之间形成用于施加偏压的触点。 形成接触以向第一阱施加阱偏置电压。

公开(公告)号：KR2020000020668U

公开(公告)日：2000-12-05

申请号：KR2019990008013

申请日：1999-05-12

Applicant: 삼성전자주식회사

Inventor： 한지훈

IPC: B65H1/00

CPC classification number: B65H1/04 ,  B65H2405/1136

Abstract: 본고안은사무용기기의출력물분류장치에관한것으로, 팩시밀리본체의배지트레이에회전가능하도록결합되는회전트레이와, 상기회전트레이를새로운출력물이출력될때마다, 소정의각도로회전시키는구동수단을포함하여구성한다. 상기와같은본 고안에의하면, 회전트레이가소정의각각의출력물을수신하는경우마다소정의각도로회전되도록함으로써여러건의출력물을수신하는경우, 다른건과섞이지않고분류를가능하다.

公开(公告)号：KR1020000066828A

公开(公告)日：2000-11-15

申请号：KR1019990014207

申请日：1999-04-21

Applicant: 삼성전자주식회사

Inventor： 한지훈

IPC: H04N1/40

CPC classification number: H04N1/4052 ,  H04N2201/0082

Abstract: PURPOSE: An error diffusion method for changing a portion of correction target pixel value randomly is provided to reject artifacts effectively so as to increase image quality. CONSTITUTION: An error diffusion method for changing a portion of correction target pixel value randomly includes following steps. A pixel to be binarized from image to be binarized is assigned in a raster scanning order(s110). Gray error value of pixels adjacent to the pixel is added to the pixel and a first correction target pixel value is calculated(s120). A predetermined portion is subtracted from the first correction target pixel value, a random number is determined in an interval from 0 to a predetermined multiple of the predetermined portion and the result is added to the first correction target pixel value to yield a second correction target pixel value(s130). Whether the second correction target pixel value is greater than an intermediate gray value is determined(s140). The target pixel is binarized to a white color when the second correction target pixel value is greater than the intermediate gray value(s150).

Abstract translation: 目的：提供用于随机改变修正目标像素值的一部分的误差扩散方法，以有效地抑制伪像，从而提高图像质量。 构成：用于随机地改变校正目标像素值的一部分的误差扩散方法包括以下步骤。 以光栅扫描顺序分配要从二值化图像二值化的像素（s110）。 将与像素相邻的像素的灰度误差值加到像素，并计算第一校正目标像素值（s120）。 从第一校正对象像素值中减去预定部分，在从0到预定部分的预定倍数的间隔中确定随机数，并将结果加到第一校正目标像素值，以产生第二校正目标像素 值（S130）。 确定第二校正目标像素值是否大于中间灰度值（s140）。 当第二校正目标像素值大于中间灰度值时，目标像素被二值化为白色（s150）。

公开(公告)号：KR1020000014963A

公开(公告)日：2000-03-15

申请号：KR1019980034615

申请日：1998-08-26

Applicant: 삼성전자주식회사

Inventor： 한지훈

IPC: H04N1/27

CPC classification number: H04N1/405 ,  H04N1/2195 ,  H04N2201/0081

Abstract: PURPOSE: The high speed image binarization apparatus is provided to achieve high speed image binarization by carrying out the image binarization and to enhance the benefit in industry by not changing the binarization module part but using it as it is. CONSTITUTION: The apparatus comprises a storage member (100) which provides a reading access and a recording access; a data buffering part(200) which outputs the data; a binarization module part(300) which carries out the image binarization corresponding to the each pixel by receiving the output of the data buffering part(200); and a binarization controlling part(400) which controls the operation timing of the module part. The bit number per pixel is eight and the storing member is the RAM which provides the random access. The waiting time of the binarization comprises four system clock.

Abstract translation: 目的：提供高速图像二值化装置，通过执行图像二值化实现高速图像二值化，并通过不改变二值化模块部分，但是直接使用它来提高工业的效益。 构成：该装置包括提供读取访问和记录访问的存储构件（100）; 数据缓冲部分（200），其输出数据; 二进制化模块部分（300），其通过接收数据缓冲部分（200）的输出来执行对应于每个像素的图像二值化; 以及控制模块部的动作定时的二值化控制部（400）。 每像素的位数为8，存储器是提供随机存取的RAM。 二进制化的等待时间包括四个系统时钟。