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公开(公告)号：KR1019930009799B1
公开(公告)日：1993-10-11
申请号：KR1019900021846
申请日：1990-12-26
Applicant: 한국전자통신연구원
Abstract: This circuit comprises flip-flops (1)(2) for supplying multiplexer (B) with latched input data (IN-ST), flip-flop (18) for latching alternately the two flip-flops (1)(2) according to the state of write signal (WR), AC (3) for outputting clear signal (CLR), full signal (FULL), or empty signal (EMPTY) according to input of reset signal (RESET), write signal (WR), or clock signal (CLOCK), and flip-flop (11) for outputting select signal of multiplexer (S) according to OR of read signal (RD), clock signal (CLOCK) or empty signal (EMPTY) of QC (3).
Abstract translation: 该电路包括用于向多路复用器（B）提供锁存的输入数据（IN-ST）的触发器（1）（2），用于根据下述方式交替地锁存两个触发器（1）（2）的触发器（18） 根据复位信号（RESET）的输入，写入信号（WR）或写入信号（WR）的写入信号（WR），用于输出清除信号（CLR）的全部信号（FULL）或空白信号（EMPTY） 时钟信号（CLOCK）和触发器（11），用于根据QC（3）的读信号（RD），时钟信号（CLOCK）或空信号（EMPTY）的OR输出多路复用器（S）的选择信号。
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Patent Agency Ranking
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公开(公告)号：KR1020150103398A
公开(公告)日：2015-09-11
申请号：KR1020140024813
申请日：2014-03-03
Applicant: 한국전자통신연구원
IPC: H04L12/46
CPC classification number: H04L67/141 , H04L41/0806
Abstract: 본 발명의 일 실시예에 따른 노드 간 통신 연결 방법은 네트워크를 통한 노드 간 통신 연결 방법에 있어서, 다른 노드들의 통신 개체들에 대한 탐색을 통해 획득되는 통신 연결 정보를 저장하는 단계, 상기 저장된 통신 연결 정보를 검색하여 연결 대상 노드의 통신 개체에 대한 통신 연결 정보가 존재하는지 판단하는 단계, 및 상기 판단 결과에 기초하여 상기 연결 대상 노드의 통신 개체와 통신 연결을 설정하는 단계를 포함한다.
Abstract translation: 本发明涉及一种用于连接节点之间的通信的方法。 根据本发明的实施例，该方法包括以下步骤：存储关于通过检测其他节点的通信实体而获得的通信连接的信息; 通过检测存储的关于通信连接的信息来确定关于连接目标节点的通信实体的通信连接的信息是否存在; 以及基于所述确定结果来设置与所述连接目标节点的通信实体的通信连接。
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公开(公告)号：KR1020030047544A
公开(公告)日：2003-06-18
申请号：KR1020010078194
申请日：2001-12-11
Applicant: 한국전자통신연구원
IPC: G06F13/24
CPC classification number: G06F13/24
Abstract: PURPOSE: A device and method for relaying an interrupt for a communication between processors is provided to transmit an interrupt received by a master processor to a slave processor and generate an interrupt for supporting communication between processors in a system on-chip design having many ARM processors. CONSTITUTION: The second ARM processor executes a master function. The first ARM processor executes a salve function. A vector interrupt control unit(400) selects many interrupt request signals according to priority and transmits the interrupt request signals to the second ARM processor(300). An interrupt relay unit(200) retransmits an interrupt to the first ARM processor(100) designated as a salve process in accordance with a request of the master processor(300) and supports a communication between processors. A master interrupt generation unit(700) is controlled by the master processor(300) and requests an interrupt to the master processor(300) using hardware. A salve interrupt generation unit(800) is controlled by the slave processor(100) and requests an interrupt to the salve processor(100) using hardware. A memory control unit(500) controls a serial port, a timer(600), and a chip external memory access. An internal bus(900) connects the above elements.
Abstract translation: 目的：提供用于中继处理器之间的通信的装置和方法，用于将由主处理器接收的中断发送到从属处理器，并产生用于支持具有许多ARM处理器的系统片上设计的处理器之间的通信的中断 。 构成：第二个ARM处理器执行主功能。 第一个ARM处理器执行一个补全功能。 向量中断控制单元（400）根据优先级选择许多中断请求信号，并将中断请求信号发送给第二ARM处理器（300）。 根据主处理器（300）的请求，中断中继单元（200）向指定为签发进程的第一ARM处理器（100）重传中断，并支持处理器之间的通信。 主中断产生单元（700）由主处理器（300）控制，并使用硬件向主处理器（300）请求中断。 药膏中断产生单元（800）由从属处理器（100）控制，并使用硬件向加药处理器（100）请求中断。 存储器控制单元（500）控制串行端口，定时器（600）和芯片外部存储器存取。 内部总线（900）连接上述元件。
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公开(公告)号：KR100205072B1
公开(公告)日：1999-06-15
申请号：KR1019960061992
申请日：1996-12-05
Applicant: 한국전자통신연구원
IPC: G06F12/00
CPC classification number: G06F11/1076 , G06F2211/1009
Abstract: A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance.
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