Abstract:
본 발명에 따르면, 입력 영상의 x축, y축 다차원 그래디언트를 이용하여 하 라이크 필터로부터 보다 다양한 특징을 추출할 수 있으며, 추출된 입력 영상의 특징과 True 영상에 대한 다중 임계값 및 False 영상에 대한 다중 임계값을 단계별로 이용하여 입력 영상을 정확하게 True/False로 분류할 수 있다. 따라서, 연산량은 적으면서도 인식률은 높아지므로 빠르면서도 정확하게 물체를 인식할 수 있어 실시간 영상 인식이 가능하다는 효과가 있다. 하 라이크(Haar like), 특징, 그래디언트, 절대값, 인식률, 연산량
Abstract:
PURPOSE: A characteristic vector classification device and a method thereof are provided to reduce calculation amount by determining recalculation by comparing an error value and an error threshold value. CONSTITUTION: A variable calculation unit(120) calculates a weighted value and errors through a value set in an initial condition setting unit. A variable calculation unit calculates a training vector. A loop determination unit(130) determines recalculation by comparing an error value and an error threshold value. A boundary surface generation unit(140) generates a boundary surface by receiving a termination signal from the loop determination unit. An error value calculated by the variable calculation unit is a standardized average square error value. [Reference numerals] (110) Initial condition setting unit; (120) Variable calculation unit; (130) Loop determination unit; (140) Boundary surface generation unit;
Abstract:
PURPOSE: A direct memory access(DMA) controller and a method for operating the same are provided to reduce the generated frequency of interrupts representing the completion of DMA transmission. CONSTITUTION: A bus interface(610) receives the DMA controlling data of a processor. A DMA transmission controlling logic(640) implements a DMA transmission operation by referring the DMA controlling data which is set in a register set unit(620). After the completion of the DMA transmission operation, the DMA transmission controlling logic generates interrupts. A DMA master interface(650) implements a physical data transmission operation. An FIFO buffer memory device(660) temporarily saves transmission data and related controlling signals in the DMA transmission operation.
Abstract:
PURPOSE: An object detecting device and a system thereof are provided to form a feature vector by using HOG(Histogram of Oriented Gradients) and pixel coordinate information . CONSTITUTION: An outline image extracting unit(120) extracts an outline image from an input image. A feature vector calculating unit(130) calculates a feature vector from the outline image by using HOG and pixel coordinate information. The HOG displays frequency distribution of gradient vectors for pixels in the outline image. The pixel coordinate information is changed by spatial distribution of the gradient vectors. An object determining unit(150) determines a target object corresponding to the feature vector referring to pre-learned data.
Abstract:
PURPOSE: An image recognition method and an image recognition device thereof are provided to offer additional memory to store a standard image and a reduced image. CONSTITUTION: An image recognition device selects a part of data from standard image data(S110). The image recognition device recognizes an image based on selected data(S120). The image recognition device reduces the selected data(S130). The image recognition device recognizes the image based on the reduced data(S140).
Abstract:
PURPOSE: A bus bridge apparatus is provided to maximize data transmission performance among interconnections, by transmitting and receiving data by considering characteristics among different interconnections. CONSTITUTION: A slave port (210) performs interface with a master device of a bus based interconnection (110), and receives read and write transmission command, address data and write data from the master device, and transmits read data to the master device. A command controller (220) receives the transmission command, and an address buffer (230) stores the address data. A write data buffer (240) stores the write data, and a read data buffer (270) stores the read data. A protocol converter (260) outputs the write data of the master device to the slave device, by using the address and write data in case of the write transmission command. [Reference numerals] (200) Bus bridge apparatus; (210) Slave port; (220) Bus based interconnection; (230) Address buffer; (240) Write data buffer; (250) Transmission mode controller; (260) Protocol converter; (270) Read data buffer; (AA) Bus based interconnection; (BB) Network based interconnection
Abstract:
PURPOSE: A pedestrian detection method of a pedestrian detection device is provided to perform pedestrian detection on a search window using a second classifier with high accuracy after reducing the number of search windows, thereby performing highly accurate detection of an object while reducing the complexity of detection procedure and power consumption. CONSTITUTION: A pedestrian detection device obtains an image from a digital image device and performs blocking of search windows(210,220). The pedestrian detection device selects a specific block from blocks determined by a pre-learned classifier(230) and produces a specific vector of HOG features from the selected block(240,250). The pedestrian detection device calculates a SVM(Support Vector Machine) response value using the produced feature vector, and performs a first object detection by applying the response value to an AdaBoost Classifier(260,270). If a pedestrian is detected at the first object detection, the pedestrian detection device performs a second object detection to the search window(280). [Reference numerals] (210) Obtain an image; (220) Performs blocking of search windows; (230) Pre-learned classifier; (240) Select a specific block; (250) Produce a specific vector; (260) Calculates a SVM response value; (270) Perform a first object detection; (280) Perform a second object detection; (290) Output decision; (AA) No; (BB) Yes
Abstract:
PURPOSE: A memory system comprising a plurality of DMA channels and an integrating management method for a plurality of DMA channels are provided to improve data transmission efficiency of a memory controller by the integrated management of multichannel memory controller and connected multiple DMA channels. CONSTITUTION: A memory controller(200) performs data transceiving operation with a memory(100). The memory controller comprises multiple channels which are physically separated each other. A DMA controller (300) is connected to the multiple channels of the memory controller and includes multiple DMA channels which are physically separated each other. The DMA controller performs data transceiving operation with the memory through the multiple DMA channels and the memory controller. An access module(400) connects the channels of the memory controller with the DMA channels each other.